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Volumn , Issue , 2004, Pages 205-208

Communication on a segmented bus platform

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SOFTWARE; DATA TRANSFER; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; THROUGHPUT;

EID: 14844337866     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (13)
  • 1
    • 14844293341 scopus 로고    scopus 로고
    • Metastability in altera devices
    • May
    • Altera Corporation. Metastability in Altera Devices. Application Note 42, May 1999.
    • (1999) Application Note , vol.42
  • 2
    • 27844493060 scopus 로고    scopus 로고
    • Techniques to make clock switching glitch free
    • August
    • Altera Corporation. Techniques to Make Clock Switching Glitch Free. White Paper, August 2001.
    • (2001) White Paper
  • 4
    • 0033097604 scopus 로고    scopus 로고
    • Segmented bus design for low-power systems
    • J. Y. Chen et al. Segmented Bus Design for Low-Power Systems. IEEE Trans. On VLSI Systems, Vol. 7, No. 1, 1999, pp. 25-29
    • (1999) IEEE Trans. on VLSI Systems , vol.7 , Issue.1 , pp. 25-29
    • Chen, J.Y.1
  • 6
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • W.J. Dally, B. Towles Route Packets, Not Wires: On-Chip Interconnection Networks. DAC 2001, pp. 684-689.
    • DAC 2001 , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 7
    • 0037218782 scopus 로고    scopus 로고
    • Design theory and implementation for low-power segmented bus systems
    • W.-B. Jone et al. Design Theory and Implementation for Low-Power Segmented Bus Systems. ACM Transactions on Design Automation of Electronic Systems, Vol. 8, Nr. 1, 2003, pp. 38-54.
    • (2003) ACM Transactions on Design Automation of Electronic Systems , vol.8 , Issue.1 , pp. 38-54
    • Jone, W.-B.1
  • 8
    • 14844317124 scopus 로고    scopus 로고
    • Bridging clock domains by synchronizing the mice in the mousetrap
    • J.J. Chico and E. Macii (Eds.): PATMOS 2003, Springer-Verlag
    • J. Kessels et al. Bridging Clock Domains by Synchronizing the Mice in the Mousetrap. J.J. Chico and E. Macii (Eds.): PATMOS 2003, Springer-Verlag, LNCS 2799, pp. 141-150.
    • LNCS , vol.2799 , pp. 141-150
    • Kessels, J.1
  • 10
    • 0348156140 scopus 로고    scopus 로고
    • Implementation of a self-timed segmented bus
    • J. Plosila et al. Implementation of a Self-Timed Segmented Bus. IEEE Design & Test of Computers, Vol. 20, Nr. 6, 2003, pp. 44-50.
    • (2003) IEEE Design & Test of Computers , vol.20 , Issue.6 , pp. 44-50
    • Plosila, J.1
  • 12
    • 33749049552 scopus 로고    scopus 로고
    • On the organization of a multi-segmented bus
    • To appear as
    • T. Seceleanu, O. Nevalainen et al. On the Organization of a Multi-segmented Bus. To appear as technical report, 2004.
    • (2004) Technical Report
    • Seceleanu, T.1    Nevalainen, O.2
  • 13
    • 0036948803 scopus 로고    scopus 로고
    • Round-robin arbiter design and generation
    • Kyoto, Japan
    • E.S. Shin et al. Round-robin Arbiter Design and Generation. ISSS'02, 2002, Kyoto, Japan.
    • (2002) ISSS'02
    • Shin, E.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.