Architectural modifications to improve floating-point unit efficiency in FPGAS

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 515-520

  Beauchamp, Michael J ^a   Hauck, Scott ^a   Underwood, Keith D ^b   Hemmert, K Scott ^b  

^a UNIVERSITY OF WASHINGTON   (United States)

^b SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

4:1 MULTIPLEXER; ARCHITECTURAL MODIFICATIONS; AREA SAVINGS; CLOCK RATES; COARSE GRAINED (CG); FIELD PROGRAMMABLE LOGIC (FPL); FLOATING POINT (FP); FLOATING-POINT OPERATIONS; FLOATING-POINT UNIT (FPU); FPGA FABRIC; INTERNATIONAL CONFERENCES; PRECISION FLOATING; VARIABLE LENGTHS;

ADDERS; CMOS INTEGRATED CIRCUITS; FABRICS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; MULTIPLEXING; MULTIPLEXING EQUIPMENT;

DIGITAL ARITHMETIC;

EID: 46249115443     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311260     Document Type: Conference Paper

References (14)

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