RASoC: A router soft-core for networks-on-chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 3, Issue , 2004, Pages 198-203

  Zeferino, Cesar Albenes ^a   Kreutz, Márcio Eduardo ^b   Susin, Altamiro Amadeu ^b  

^a UNIVERSIDADE DO VALE DO ITAJAÍ   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKES; DIFFERENT SIZES; NETWORK ON CHIP; NETWORKS ON CHIPS; PARAMETERIZED; ROUTER ARCHITECTURE; TARGET APPLICATION; VHDL MODELING;

EXHIBITIONS; NETWORK ARCHITECTURE; VLSI CIRCUITS;

ROUTERS;

EID: 84893807061     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269230     Document Type: Conference Paper

References (9)

1. L. Benini and G. De Micheli, "Networks on Chips: a New SOC Paradigm", IEEE Computer, Jan. 2002, pp.70-78.
2. P. Guerrier and A. Greiner, "A Generic Architecture for on-Chip Packet-Switched Interconnections", DATE'2000, IEEE CS Press, 2000. pp.250-256.
3. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", DAC'2001, ACM Press, 2001. pp.684-689.
4. S. Kumar et al., "A Network on Chip Architecture and Design Methodology", Annual Symposium on VLSI'2002, IEEE CS Press, 2002. pp.105-112.
5. J. Duato et al., Interconnection Networks: an Engineering Approach, IEEE CS Press, 1997. 515p.
6. J. C. B. Mattos and L. Carro. "Efficient Architecture for FPGA-based Microcontrollers". ISCAS'2002, IEEE CS Press, v.5, 2002. p.805-808.
7. F. Petrot et al. "Cycle-Precise Core Based Hardware/Software System Simulation with Predictable Event Propagation", EUROMICRO'1997, IEEE CS Press, 1997. p.182-187.
8. Siemens. "OMI 324: PI-Bus-Ver.0.3d", Siemens AG, 1994. 35p.
9. A. Andriahantenaina et al. "SPIN: A Scalable, Packet Switched On-Chip Micro-Network". DATE'2003, IEEE CS Press, 2003. p.70-73.