LiPaR: A light-weight parallel router for FPGA-based networks-on-chip

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 452-457

  Sethuraman, Balasubramanian ^a   Bhattacharya, Prasun ^a   Khan, Jawad ^a   Vemuri, Ranga ^a  

^a University of Cincinnati   (United States)

Author keywords

FPGA; Networks on Chip; Router; SoC

Indexed keywords

LIGHT-WEIGHT PARALLEL ROUTER; NETWORKS-ON-CHIP; ROUTING;

ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON;

ROUTERS;

EID: 29244474650     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. Altera Inc. http://www.altera.com.
2. L. Benini and G. De Micheli. Networks on Chips: A New SOC Paradigm. In IEEE Computer, pages 70-78, Jan. 2002.
3. D.M. Chapiro. Globally Asynchronous Locally Synchronous Systems. PhD thesis, 1984.
4. W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Design Automation Conference, pages 684-689, 2001.
5. J. Duato and L. Ni S. Yalamanchili. Interconnect Networks: An Engineering Approach. In IEEE CS Press, 1998.
6. A. Hemani et. al. Network on Chip: An architecture for billion transistor era. In IEEE NorChip Conference, November 2000.
7. Fernando Moraes et. al. A Low Area Overhead Packet-switched Network On Chip: Architecture and Prototyping. In IFIP VLSI-SOC 2003, pages 318-323, 2003.
8. S. Kumar et al. A Network on Chip Architecture and Design Methodology. In Annual Symposium on VLSI'2002, IEEE CS Press, pages 105-112, 2002.
9. T.A. Bartic et al. Highly Scalable Network on Chip for Reconfigurable Systems. In Proceedings of the International Conference on System-On-Chip 2003, pages 79-82, Nov. 2003.
10. Theodore Marescaux et. al. Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGAs. In FPL '2002, pages 795-805, September 2002.
11. Nikolay Kavaldjiev and Gerard J.M. Smit. A survey of efficient on-chip communications for SoC. In PROGRESS 2003 Embedded Systems Symposium, October 2003.
12. Nikolay Kavaldjiev and Gerard J.M. Smit. An energy-efficient Network-on-chip for a heterogeneous tiled reconfigurable Systems-on-Chip. In EURO MICRO Symposium on Digital System Design, pages 492-498, September 2004.
13. MentorGraphics Inc. http://www.mentorgraphics.com.
14. International Sematech. International Technology Roadmap for Semiconductors - 2002 Update. In http://public.itrs.net, 2002.
15. Xilinx Inc. http://www.xilinx.com, 2004.
16. C.A. Zerferino, M.E. Kreutz, and A.A. Susin. RASoC: A Router Soft-Core for Networks-on-Chip. In DATE'2004-Designer's Forum. IEEE CS Press, 2004.
17. C.A. Zerferino and A.A. Susin. SoCIN: A Parametric and Scalable Network on Chip. In SBCCI'2003, pages 169-174. IEEE CS Press, 2003.