Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

IEEE Transactions on Electron Devices

Volumn 53, Issue 4, 2006, Pages 706-711

  Kumar, Mamidala Jagadesh ^a   Gupta, Sumeet Kumar ^a   Venkataraman, Vivek ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

High k gate dielectric; Insulated gate field effect transistors (FETs); Internal fringe capacitance; Silicon on insulator (SOI) MOSFET; Threshold voltage; Two dimensional (2 D) modeling

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRODES; NANOTECHNOLOGY; PERMITTIVITY; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

HIGH-K GATE DIELECTRIC; INTERNAL FRINGE CAPACITANCE; SILICON-ON-INSULATOR (SOI) MOSFET;

MOSFET DEVICES;

EID: 33645740144     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.870424     Document Type: Article

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