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E. Morifuji, M. Kanda, N. Yanagiya, S. Matsuda, S. Inaba, K. Okano, K. Takahashi, M. Nishigori, H. Tsuno, T. Yamamoto, K. Hiyama, M. Takayanagi, H. Oyamatsu, S. Yamada, T. Noguchi, and M. Kakumu, "High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)," in IEDM Tech. Dig., 2002, pp. 655-658.
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M. Fujiwara, M. Takayanagi, T. Shimizu, and Y. Toyoshima, "Extending gate dielectric scaling limit by NO oxynitride: Design and process issues for sub-100 nm technology," in IEDM Tech. Dig., 2000, pp. 227-230.
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