Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2006, Pages 252-255

  Zhao, Hui ^a   Agrawal, Naveen ^a   Javier, Ramos ^b   Rustagi, Subhash C ^c   Jurczak, M ^b   Yeo, Yee Chia ^a   Samudra, Ganesh S ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b IMEC   (Belgium)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

3D simulation; Capacitance; FinFET; Multi gate; Scaling

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC RESISTANCE; MOSFET DEVICES;

CURRENT CROWDING EFFECT; FINFET DEVICE; PITCH SCALING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 42549148018     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2006.282883     Document Type: Conference Paper

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