Fabrication of FinFETs by damage-free neutral-beam etching technology

IEEE Transactions on Electron Devices

Volumn 53, Issue 8, 2006, Pages 1826-1833

  Endo, Kazuhiko ^a   Noda, Shuichi ^b   Masahara, Meishoku ^a   Kubota, Tomohiro ^b   Ozaki, Takuya ^b   Samukawa, Seiji ^b   Liu, Yongxun ^a   Ishii, Kenichi ^a   Ishikawa, Yuki ^a   Sugimata, Etsuro ^a   Matsukawa, Takashi ^a   Takashima, Hidenori ^a   Yamauchi, Hiromi ^a   Suzuki, Eiichi ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

Carrier mobility; Damaged free; Double gate MOSFET (DG MOSFET); Neutral beam (NB); Utrathin channel fabrication

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; ELECTRON MOBILITY; ETCHING; SEMICONDUCTOR DEVICE MANUFACTURE;

DAMAGED-FREE; DOUBLE-GATE MOSFET (DG-MOSFET); NEUTRAL BEAM (NB); ULTRATHIN-CHANNEL FABRICATION;

MOSFET DEVICES;

EID: 33746612899     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.877035     Document Type: Article

References (19)

1. T. Sekigawa and Y. Hayashi, "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate," Solid State Electron., vol. 27, no. 8/9, pp. 827-828, 1984.
2. M. Masahara, Y. Liu, S. Hosokawa, T. Matsukawa, K. Ishii, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki, "Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching," IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2078-2085, Dec. 2004.
3. Y. Liu, M. Masahara, K. Ishii, T. Sekigawa, H. Takashima, H. Yamauchi, and E. Suzuki, "A highly threshold voltage-controllable 4T FinFET with 8.5-nm-thick Si-Fin channel," IEEE Electron Device Lett., vol. 25, no. 7, pp. 510-512, Jul. 2004.
4. 2 reactive ion etching," Appl. Phys. Lett., vol. 45, no. 4, pp. 420-422, Aug. 1984.
5. C. J. Petti, J. P. McVitte, and J. D. Plummer, "Characterization of surface mobility on the sidewall of dry etched trenches," in IEDM Tech. Dig., 1988, pp. 104-107.
6. F. Shimokawa, Y. Ishikawa, and M. Okigawa, "On-wafer monitoring of vacuum-ultraviolet radiation damage in high-density plasma processes," Jpn. J. Appl. Phys., vol. 40, no. 12B, pp. L1346-L1348, Dec. 2001.
7. F. Shimokawa, "High-power fast-atom beam source and its application to dry etching," J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 10, no. 4, pp. 1352-1357, Jul. 1992.
8. T. Yunogami, K. Yokogawa, and T. Mizutani, "Development of neutral-beam-assisted etcher," J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 13, no. 3, pp. 952-958, May 1995.
9. S. Samukawa, K. Sakamoto, and K. Ichiki, "Generating high-efficiency neutral beams by using negative ions in an inductively coupled plasma source," J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 20, no. 5, pp. 1566-1573, Sep. 2002.
10. S. Noda, H. Nishimori, T. Ida, T. Arikado, K. Ichiki, T. Ozaki, and S. Samukawa, "50-nm gate electrode patterning using a neutral-beam etching system," J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 22, no. 4, pp. 1506-1512, Jul. 2004.
11. K. Endo, M. Masahara, Y. X. Liu, T. Matsukawa, K. Ishii, E. Sugimata, H. Takashima, H. Yamauchi, and E. Suzuki, "Investigation of N-channel triple-gate MOSFETs on (100) SOI substrate," in Proc. Ext. Abst. Solid State Devices Mater., 2005, p. 276.
12. M. Masahara, S. Hosokawa, T. Matsukawa, K. Endo, Y. Naitou, H. Tanoue, and E. Suzuki, "Dopant profiling in vertical ultrathin channels of double-gate metal-oxide-semiconductor field-effect transistors by using scanning nonlinear dielectric microscopy," Appl. Phys. Lett., vol. 85, no. 18, pp. 4139-4141, Nov. 2004.
13. M. Koh-Masahara, K. Esuga, H. Furumoto, T. Shirahata, E. Seo, K. Shibahara, S. Yokoyama, and M. Hirose, "Quantitative evaluation of dopant loss in 5-10 keV as ion implantation for low-resistive, ultrashallow source/drain formation," Jpn. J. Appl. Phys. 1, Regul. Rap. Short Notes, vol. 38, no. 4B, pp. 2324-2328, Apr. 1999.
14. F. Shimokawa and H. Kuwano, "Energy distribution and formation mechanism of fast atoms in a fast atom beam," J. Appl. Phys., vol. 72, no. 1, pp. 13-17, Jul. 1992.
15. H. Irie, K. Kita, K. Kyuno, and A. Toriumi, "In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layer on (100), (110), and (111) Si," in IEDM Tech. Dig., 2004, pp. 225-228.
16. D. K. Schroder, Semiconductor Material and Device Characterization. New York: Wiley, 1998.
17. J. Koga, S. Takagi, and A. Toriumi, "A comprehensive study of MOSFET electron mobility in both weak and strong inversion regimes," in IEDM Tech. Dig., 1994, pp. 475-478.
18. F. Gámiz, J. B. Roldán, P. Cartujo-Cassinello, J. A. López-Villanueva, and P. Cartujo, "Role of surface-roughness scattering in double gate silicon-on-insulator inversion layers," J. Appl. Phys., vol. 89, no. 3, pp. 1764-1770, Feb. 2001.
19. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part II - Effects of surface orientation," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2363-2368, Dec. 1994.