-
1
-
-
0001853125
-
The computer for the twenty-first century
-
September
-
Mark Weiser. The Computer for the Twenty-First Century Scientific American, pages 94-110, September 1991
-
(1991)
Scientific American
, pp. 94-110
-
-
Weiser, M.1
-
2
-
-
4143142037
-
-
SIA roadmap 2003 http://public.itrs.net
-
(2003)
SIA Roadmap
-
-
-
3
-
-
4143143245
-
Adaptive architectures for an OTN processor: Reducing design costs through reconfigurability and multiprocessing
-
April . Ischia, Italy
-
T. Murgan, M. Petrov, U. Heinkel, M. Majer, J. Pleickhardt, B. Bleisteiner, P. Zipf, and M. Glesner. Adaptive Architectures for an OTN Processor: Reducing Design Costs Through Reconfigurability and Multiprocessing. In ACM Computing Frontiers Conference,. April 2004. Ischia, Italy.
-
(2004)
ACM Computing Frontiers Conference
-
-
Murgan, T.1
Petrov, M.2
Heinkel, U.3
Majer, M.4
Pleickhardt, J.5
Bleisteiner, B.6
Zipf, P.7
Glesner, M.8
-
4
-
-
0030714347
-
Reconfigurable processing: The solution to low-power programmable DSP
-
April
-
J. Rabaey. Reconfigurable Processing: The Solution to Low-Power Programmable DSP. In IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, volume 1, pages 275-278, April 1997.
-
(1997)
IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing
, vol.1
, pp. 275-278
-
-
Rabaey, J.1
-
5
-
-
0033706197
-
A survey of design techniques for system-level dynamic power management
-
June
-
L. Benini, A. Bogliolo, and G. D. Micheli. A survey of design techniques for system-level dynamic power management. IEEE Transactions on VLSI, 8(3):299-316, June 2000.
-
(2000)
IEEE Transactions on VLSI
, vol.8
, Issue.3
, pp. 299-316
-
-
Benini, L.1
Bogliolo, A.2
Micheli, G.D.3
-
6
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
Jan
-
L. Benini and G. D. Micheli. Networks on Chips: A New SoC Paradigm. IEEE Computer, Vol. 35:70-78, Jan 2002.
-
(2002)
IEEE Computer
, vol.35
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
8
-
-
0015600423
-
The viterbi algorithm
-
March
-
G. D. Forney. The viterbi algorithm. Proceedings IEEE, 61(3):218-278, March 1973.
-
(1973)
Proceedings IEEE
, vol.61
, Issue.3
, pp. 218-278
-
-
Forney, G.D.1
-
9
-
-
21644460341
-
An adaptive trace-back solution for state-parallel viterbi decoders
-
Seeheim, Germany, Dec
-
M. Petrov, A. Obeid, and T. Murgan. An adaptive trace-back solution for state-parallel viterbi decoders. In VLSI-SoC Conference, pages 167-173, Seeheim, Germany, Dec. 2003.
-
(2003)
VLSI-SoC Conference
, pp. 167-173
-
-
Petrov, M.1
Obeid, A.2
Murgan, T.3
-
10
-
-
0034846659
-
Addressing the system-on-a-chip interconnect woes through communication-based design
-
M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiqvanni-Vincentelli. Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. In Proc. of the Design Automation Conference (DAC 2001), pages 667-672, 2001.
-
(2001)
Proc. of the Design Automation Conference (DAC 2001)
, pp. 667-672
-
-
Sgroi, M.1
Sheets, M.2
Mihal, A.3
Keutzer, K.4
Malik, S.5
Rabaey, J.6
Sangiqvanni-Vincentelli, A.7
-
11
-
-
0026823944
-
A VLSI design for a trace-back viterbi decoder
-
March
-
T. K. Truong, M. Shih, I. S. Reed, and E. H. Satorius. A VLSI design for a trace-back viterbi decoder. IEEE Transactions on Communications, 40(3):616-624, March 1992.
-
(1992)
IEEE Transactions on Communications
, vol.40
, Issue.3
, pp. 616-624
-
-
Truong, T.K.1
Shih, M.2
Reed, I.S.3
Satorius, E.H.4
-
12
-
-
84935113569
-
Error bounds for convolutional codes and an asymptotically optimum decoding algorithm
-
A. J. Viterbi. Error bounds for convolutional codes and an asymptotically optimum decoding algorithm. IEEE Transactions on Information Theory, 11-13:260-269, 1967.
-
(1967)
IEEE Transactions on Information Theory
, vol.11-13
, pp. 260-269
-
-
Viterbi, A.J.1
-
13
-
-
0003083316
-
Low-power channel coding via dynamic reconfiguration
-
March
-
M. Goel and N. Shanbhag. Low-power channel coding via dynamic reconfiguration. Proceedings of ICASSP, pages 1893-1896, March 1999.
-
(1999)
Proceedings of ICASSP
, pp. 1893-1896
-
-
Goel, M.1
Shanbhag, N.2
-
14
-
-
84893737717
-
Networks on silicon: Combining best-effort and guaranteed services
-
K. Goossens, J. van Meerbergen, A. Peeters, and P. Wielage. Networks on Silicon: Combining Best-Effort and Guaranteed Services. In Proc. of Automation and Test in Europe Conference and Exhibition 2002, pages 423-425, 2002.
-
(2002)
Proc. of Automation and Test in Europe Conference and Exhibition 2002
, pp. 423-425
-
-
Goossens, K.1
Van Meerbergen, J.2
Peeters, A.3
Wielage, P.4
-
15
-
-
0036948940
-
Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations
-
August
-
R. Henning and C. Chakrabarti. Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations. In Proceedings of ISLPED, pages 68-71, August 2002.
-
(2002)
Proceedings of ISLPED
, pp. 68-71
-
-
Henning, R.1
Chakrabarti, C.2
-
16
-
-
0032022689
-
Low-power viterbi decoder for CDMA mobile terminals
-
March
-
I. Kang and A. N. Willson. Low-power viterbi decoder for CDMA mobile terminals. In IEEE Journal of Solid-State Circuits, 33(3):473-482, March 1998.
-
(1998)
IEEE Journal of Solid-state Circuits
, vol.33
, Issue.3
, pp. 473-482
-
-
Kang, I.1
Willson, A.N.2
-
17
-
-
0034428118
-
System-level design: Orthononalization of concerns and platform-based design
-
Dec
-
K. Keuter, S. Malik, R. A. Newton, J. M. Rabaey, and A. Sangiovanni-Vincentelli. System-Level Design: Orthononalization of Concerns and Platform-Based Design. In IEEE Transactions on Computer-Aided Design of integrated Circuits and Systems, 19(12):1523-1543, Dec 2000.
-
(2000)
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
, vol.19
, Issue.12
, pp. 1523-1543
-
-
Keuter, K.1
Malik, S.2
Newton, R.A.3
Rabaey, J.M.4
Sangiovanni-Vincentelli, A.5
-
18
-
-
84948696213
-
A network on chip architecture and design methodology
-
S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Öberg, K. Tiensyrjä, and A. Hemani. A Network on Chip Architecture and Design Methodology. In Proc. of VLSI Annual Symposium (ISVLSI 2002), pages 105-112, 2002.
-
(2002)
Proc. of VLSI Annual Symposium (ISVLSI 2002)
, pp. 105-112
-
-
Kumar, S.1
Jantsch, A.2
Soininen, J.-P.3
Forsell, M.4
Millberg, M.5
Öberg, J.6
Tiensyrjä, K.7
Hemani, A.8
-
19
-
-
0022141776
-
Fat trees: Universal networks for hardware-efficient supercomputing
-
Oct
-
C. Leiserson. Fat Trees: Universal Networks for Hardware-Efficient Supercomputing. In IEEE Transaction on Computers, Vol. C-34(No. 10):892-901, Oct 1985.
-
(1985)
IEEE Transaction on Computers
, vol.C-34
, Issue.10
, pp. 892-901
-
-
Leiserson, C.1
-
22
-
-
0000227930
-
Reconfigurable computing: A survey of systems and software
-
June
-
Compton, Katherine; Hauck, Scott: Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, vol. 34, no. 2, June 2002
-
(2002)
ACM Computing Surveys
, vol.34
, Issue.2
-
-
Compton, K.1
Hauck, S.2
-
23
-
-
0036709503
-
Reconfigurable instruction set processors from a hardware/software perspective
-
September
-
Barat, Francisco; Lauwereins, Rudy; Deconinck, Geert: Reconfigurable Instruction Set Processors from a Hardware/Software Perspective, IEEE Transaction on Software Engineering, vol. 28, issue 9, September 2002
-
(2002)
IEEE Transaction on Software Engineering
, vol.28
, Issue.9
-
-
Barat, F.1
Lauwereins, R.2
Deconinck, G.3
-
25
-
-
0034174010
-
Video image processing with the sonic architecture, computer: Innovative technology for computer professionals
-
April
-
Haynes, Simon D.; Cheung, Peter Y.K.; Luk, Wayne: Video Image Processing with the Sonic Architecture, Computer: Innovative Technology for Computer Professionals, vol. 33, no.4, IEEE Computer Society, April 2000
-
(2000)
IEEE Computer Society
, vol.33
, Issue.4
-
-
Haynes, S.D.1
Cheung, P.Y.K.2
Luk, W.3
-
26
-
-
0027847339
-
The splash 2 processor and applications
-
Oktober
-
Arnold, Jeffrey M.; Buell, Duncan A.; Hoang, Dzung T.; Pryor, Daniel V.; Shirazi, Nabeel; Thistle, Mark R.: The Splash 2 Processor and Applications, Proceeding of the IEEE International Conference on VLSI in Computers and Processors (ICCD'9S), Oktober 1993
-
(1993)
Proceeding of the IEEE International Conference on VLSI in Computers and Processors (ICCD'9S)
-
-
Arnold, J.M.1
Buell, D.A.2
Hoang, D.T.3
Pryor, D.V.4
Shirazi, N.5
Thistle, M.R.6
-
28
-
-
84950155001
-
The NAPA adaptive processsing architectures
-
Rupp, Charle R.; Landguth Mark; Garverick, Tim; Gomersall, Edson; Holt, Harry; Arnold, Jeffrey M; Gokhale, Maya: The NAPA Adaptive Processsing Architectures, IEEE Symposium on Field Programmable Custom Computing Machines, 1998
-
(1998)
IEEE Symposium on Field Programmable Custom Computing Machines
-
-
Rupp, C.R.1
Mark, L.2
Garverick, T.3
Gomersall, E.4
Holt, H.5
Arnold, J.M.6
Gokhale, M.7
-
32
-
-
0031376640
-
The chimaera reconfigurable function unit
-
April
-
Hauck, Scott; Fry, Thomas W.; Hosler, Matthew M.; Kao, Jeffrey P.: The Chimaera Reconfigurable Function Unit, Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'97), April 1997
-
(1997)
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'97)
-
-
Hauck, S.1
Fry, T.W.2
Hosler, M.M.3
Kao, J.P.4
-
34
-
-
0000227930
-
Reconfigurable computing: A survey of systems and software
-
K. Compton, S. Hauck. Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys, 34 (2), pp. 171-210, 2002.
-
(2002)
ACM Computing Surveys
, vol.34
, Issue.2
, pp. 171-210
-
-
Compton, K.1
Hauck, S.2
-
36
-
-
0003683068
-
-
Reading: Addison-Wesley, 1999
-
K. Arnold, A. Wollrath, B. O'Sullivan, R. Scheifler, J. Waldo. The Jini specification. Reading: Addison-Wesley, 1999.
-
The Jini Specification
-
-
Arnold, K.1
Wollrath, A.2
O'Sullivan, B.3
Scheifler, R.4
Waldo, J.5
-
38
-
-
0003400120
-
-
Java Series. Reading: Addison Wesley
-
E. Freeman, S. Hupfer, K. Arnold. Java Spaces: principles, patterns, and pratice. Java Series. Reading: Addison Wesley, 1999.
-
(1999)
Java Spaces: Principles, Patterns, and Pratice
-
-
Freeman, E.1
Hupfer, S.2
Arnold, K.3
|