Adaptive architectures for an OTN processor: Reducing design costs through reconfigurability and multiprocessing

2004 Computing Frontiers Conference

Volumn , Issue , 2004, Pages 404-418

  Murgan, Tudor ^a   Petrov, Mihail ^a   Majer, Mateusz ^a   Zipf, Peter ^a   Glesner, Manfred ^a   Heinkel, Ulrich ^b   Pleickhardt, Joerg ^b   Bleisteiner, Bernd ^b  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

ITU T G.709; Multiprocessor and Reconfigurable Architectures; Optical Transport Networks; Standard Upgrades

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; DENSE WAVELENGTH DIVISION MULTIPLEXING; FIELD PROGRAMMABLE GATE ARRAYS; INTELLECTUAL PROPERTY; MULTIPROCESSING SYSTEMS; SERVERS;

ARCHITECHTURAL EXTENSIONS; MULTIPROCESSOR AND RECONFIGURABLE ARCHITECHTURES; OPTICAL TRANSPORT NETWORKS (OTN); SINGLE-PROCESSOR BASED SOLUTIONS; STANDARD UPGRADES;

COMPUTER SYSTEMS;

EID: 4143143245     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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