-
1
-
-
0002731162
-
Design challenges for new application-specific processors
-
Apr.
-
M.F. Jacome and G. de Veciana, "Design Challenges for New Application-Specific Processors," IEEE Design & Test of Computers, vol. 17, no. 2, pp. 40-50, Apr. 2000.
-
(2000)
IEEE Design & Test of Computers
, vol.17
, Issue.2
, pp. 40-50
-
-
Jacome, M.F.1
De Veciana, G.2
-
3
-
-
0027561268
-
Processor reconfiguration through instruction-set metamorphosis
-
Mar.
-
P.M. Athanas and H.F. Silverman, "Processor Reconfiguration through Instruction-Set Metamorphosis," Computer, pp. 11-18, Mar. 1993.
-
(1993)
Computer
, pp. 11-18
-
-
Athanas, P.M.1
Silverman, H.F.2
-
4
-
-
84957917534
-
PRISM-II compiler and architecture
-
M. Wazlowski, L. Agarwal, A. Smith, E. Lam, P. Athanas, H. Silverman, and S. Ghosh, "PRISM-II Compiler and Architecture," Proc. Workshop FPGAs and Custom Computing Machines (FCCM '93), pp. 29-16, 1993.
-
(1993)
Proc. Workshop FPGAs and Custom Computing Machines (FCCM '93)
, pp. 29-16
-
-
Wazlowski, M.1
Agarwal, L.2
Smith, A.3
Lam, E.4
Athanas, P.5
Silverman, H.6
Ghosh, S.7
-
5
-
-
0028746550
-
The nano processor: A low resource reconfigurable processor
-
M.J. Wirthlin, B.L. Hutchings, and K.L. Gilson, "The Nano Processor: A Low Resource Reconfigurable Processor," Proc. Workshop FPGAs and Custom Computing Machines (FCCM '94), pp. 23-30, 1994.
-
(1994)
Proc. Workshop FPGAs and Custom Computing Machines (FCCM '94)
, pp. 23-30
-
-
Wirthlin, M.J.1
Hutchings, B.L.2
Gilson, K.L.3
-
6
-
-
0028768023
-
A high-performance microarchitecture with hardware-programmable functional units
-
Nov.
-
R. Razdan and M.D. Smith, "A High-Performance Microarchitecture with Hardware-Programmable Functional Units," Proc. 27th Int'l Symp. Microarchitecture (MICRO 27), pp. 172-180, Nov. 1994.
-
(1994)
Proc. 27th Int'l Symp. Microarchitecture (MICRO 27)
, pp. 172-180
-
-
Razdan, R.1
Smith, M.D.2
-
10
-
-
0031376640
-
The chimaera reconfigurable functional unit
-
S. Hauck, T. Fry, M. Hosler, and J. Kao, "The Chimaera Reconfigurable Functional Unit," Proc. Workshop FPGAs and Custom Computing Machines (FCCM '97), pp. 87-96, 1997.
-
(1997)
Proc. Workshop FPGAs and Custom Computing Machines (FCCM '97)
, pp. 87-96
-
-
Hauck, S.1
Fry, T.2
Hosler, M.3
Kao, J.4
-
11
-
-
84950155001
-
The NAPA adaptive processing architecture
-
C.R. Rupp, M. Landguth, T. Garverick, E. Gomersall, and H. Holt, "The NAPA Adaptive Processing Architecture," Proc. Workshop FPGAs and Custom Computing Machines (FCCM '98), pp. 28-37, 1998.
-
(1998)
Proc. Workshop FPGAs and Custom Computing Machines (FCCM '98)
, pp. 28-37
-
-
Rupp, C.R.1
Landguth, M.2
Garverick, T.3
Gomersall, E.4
Holt, H.5
-
14
-
-
0032674517
-
PipeRench: A coprocessor for streaming multimedia acceleration
-
May
-
S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, and R. Laufer, "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," Proc. 26th Int'l Symp. Computer Architecture (ISCA '99), pp. 28-39, May 1999.
-
(1999)
Proc. 26th Int'l Symp. Computer Architecture (ISCA '99)
, pp. 28-39
-
-
Goldstein, S.C.1
Schmit, H.2
Moe, M.3
Budiu, M.4
Cadambi, S.5
Taylor, R.R.6
Laufer, R.7
-
16
-
-
0029697471
-
Address calculation for retargetable compilation and exploration of instruction-set architectures
-
June
-
C. Liem, P. Paulin, and A. Jerraya, "Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures," Proc. Design Automation Conf., pp. 597-600, June 1996.
-
(1996)
Proc. Design Automation Conf.
, pp. 597-600
-
-
Liem, C.1
Paulin, P.2
Jerraya, A.3
-
17
-
-
0030171884
-
Architecture of FPGAs and CPLDs: A tutorial
-
S. Brown and J. Rose, "Architecture of FPGAs and CPLDs: A Tutorial," IEEE Design and Test of Computers, vol. 13, no. 2, pp. 42-55, 1996.
-
(1996)
IEEE Design and Test of Computers
, vol.13
, Issue.2
, pp. 42-55
-
-
Brown, S.1
Rose, J.2
-
19
-
-
85013779657
-
Specifying and compiling applications for RaPiD
-
D.C. Cronquist, P. Franklin, S.G. Berg, and C. Ebeling, "Specifying and Compiling Applications for RaPiD," Proc. Workshop FPGAs and Custom Computing Machines (FCCM '98), pp. 116-127, 1998.
-
(1998)
Proc. Workshop FPGAs and Custom Computing Machines (FCCM '98)
, pp. 116-127
-
-
Cronquist, D.C.1
Franklin, P.2
Berg, S.G.3
Ebeling, C.4
-
21
-
-
0001944474
-
Precise interrupts
-
Feb.
-
M. Moudgill and S. Vassiliadis, "Precise Interrupts," IEEE Micro, vol. 16, no. 1, pp. 58-67, Feb. 1996.
-
(1996)
IEEE Micro
, vol.16
, Issue.1
, pp. 58-67
-
-
Moudgill, M.1
Vassiliadis, S.2
-
26
-
-
0028753892
-
PRISC software acceleration techniques
-
Oct.
-
R. Razdan, K. Brace, and M.D. Smith, "PRISC Software Acceleration Techniques," Proc. Int'l Conf. Computer Design: VLSI in Computers and Processors (ICCD '94), pp. 145-149, Oct. 1994.
-
(1994)
Proc. Int'l Conf. Computer Design: VLSI in Computers and Processors (ICCD '94)
, pp. 145-149
-
-
Razdan, R.1
Brace, K.2
Smith, M.D.3
-
29
-
-
0034174174
-
The garp architecture and C compiler
-
Apr.
-
T.J. Callahan, J.R. Hauser, and J. Wawrzynek, "The Garp Architecture and C Compiler," Computer, vol. 33, no. 44, pp. 62-69, Apr. 2000.
-
(2000)
Computer
, vol.33
, Issue.44
, pp. 62-69
-
-
Callahan, T.J.1
Hauser, J.R.2
Wawrzynek, J.3
-
30
-
-
0034174187
-
PipeRench: A reconfigurable architecture and compiler
-
Apr.
-
S.C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R.R. Taylor, "PipeRench: A Reconfigurable Architecture and Compiler," Computer, vol. 33, no. 4, pp. 70-77, Apr. 2000.
-
(2000)
Computer
, vol.33
, Issue.4
, pp. 70-77
-
-
Goldstein, S.C.1
Schmit, H.2
Budiu, M.3
Cadambi, S.4
Moe, M.5
Taylor, R.R.6
-
32
-
-
0033488529
-
ConCISe: A compiler-driven CPLD-based instruction set accelerator
-
B. Kastrup, A. Bink, and J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator," Proc. Workshop FPGAs and Custom Computing Machines (FCCM '99), pp. 92-101, 1999.
-
(1999)
Proc. Workshop FPGAs and Custom Computing Machines (FCCM '99)
, pp. 92-101
-
-
Kastrup, B.1
Bink, A.2
Hoogerbrugge, J.3
-
33
-
-
0032593115
-
3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems
-
July
-
K. Bazargan, R. Kastner, and M. Sarrafzadeh, "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems," Proc. 10th Int'l Workshop Rapid System Prototyping (RSP '99), pp. 38-43, July 1999.
-
(1999)
Proc. 10th Int'l Workshop Rapid System Prototyping (RSP '99)
, pp. 38-43
-
-
Bazargan, K.1
Kastner, R.2
Sarrafzadeh, M.3
-
34
-
-
0031098939
-
Embedded software in real-time signal processing systems: Design technologies
-
Mar.
-
G. Goossens, J. Van Praet, D. Lanneer, W. Geurts, A. Kifli, C. Liem, and P.G. Paulin, "Embedded Software in Real-Time Signal Processing Systems: Design Technologies," Proc. IEEE, vol. 85, no. 3, pp. 436-454, Mar. 1997.
-
(1997)
Proc. IEEE
, vol.85
, Issue.3
, pp. 436-454
-
-
Goossens, G.1
Van Praet, J.2
Lanneer, D.3
Geurts, W.4
Kifli, A.5
Liem, C.6
Paulin, P.G.7
-
36
-
-
0028743437
-
Compiler transformations for high-performance computing
-
Dec.
-
D.F. Bacon, S.L. Graham, and O.J. Sharp, "Compiler Transformations for High-Performance Computing," ACM Computing Surveys, vol. 26, no. 4, pp. 345-420, Dec. 1994.
-
(1994)
ACM Computing Surveys
, vol.26
, Issue.4
, pp. 345-420
-
-
Bacon, D.F.1
Graham, S.L.2
Sharp, O.J.3
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