PCI-PipeRench and the SwordAPI: A system for stream-based reconfigurable computing

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1999, Pages 200-208

  Laufer, Ronald ^a   Taylor, R Reed ^a   Schmit, Herman ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; NETWORK PROTOCOLS; PIPELINE PROCESSING SYSTEMS;

APPLICATION PROGRAMMING INTERFACE; HARDWARE SIMULATOR; RECONFIGURABLE HARDWARE ACCELERATORS;

INTERFACES (COMPUTER);

EID: 0033488536     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Annapolis Micro Systems, Inc. WILD-ONE™ Reference Manual. Revision 3.1. 1998.
2. P. Bellows and B. Hutchings. JHDL - An HDL for Reconfigurable Systems. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, pages 175-184, Napa Valley, CA, April 1998.
3. R. Bittner and P. Athanas. Wormhole Run-Time Reconfiguration. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 79-85, Monterey, CA, February 1997.
4. V. M. Bove, Jr. and J. A. Watlington. Cheops: A Reconfigurable Data-Flow System for Video Processing, IEEE Transactions on Circuits and Systems for Video Technology, pages 140-149, April 1995.
5. S. Cadambi, J. Weener, S.C. Goldstein, H. Schmit, and D. Thomas. Managing Pipeline-Reconfigurable FPGAs. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 55-64, Monterey, CA, February 1998.
6. S. L. Coumeri and D. E. Thomas. A Simulation Environment for Hardware-Software Codesign. International Conference on Computer Design, October 1995.
7. S. Crago, B. Schott, R. Parker. SLAAC: A Distributed Architecture for Adaptive Computing. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, pages 286-287, Napa Valley, CA, April 1998.
8. S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. Taylor, R. Laufer. PipeRench: A Coprocessor for the Future. In International Symposium on Computer Architecture, Atlanta, GA June 1999. To be published.
9. M. Moe, H. Schmit, S.C. Goldstein. Characterization and Parameterization of a Pipeline Reconfigurable FGPA. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, pages 294-295, Napa Valley, CA, April 1998.
10. J. Rose and D. Hill. Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 129-132, Monterey, CA, February 1997.
11. H. Schmit. Incremental reconfiguration for pipelined applications. In Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 47-55, Napa Valley, CA, April 1997.