LOW-POWER CHANNEL CODING VIA DYNAMIC RECONFIGURATION

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 4, Issue , 1999, Pages 1893-1896

  Goel, Manish ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CHANNEL CODING; DYNAMIC MODELS; SIGNAL TO NOISE RATIO;

BIT-ERROR RATE; DYNAMIC RE-CONFIGURATION; ENERGY; ENERGY SAVINGS; ENERGY-SAVINGS; FINITE FIELDS ARITHMETIC; GATE LEVELS; LOW POWER; OBJECTIVE FUNCTIONS; POWER CHANNELS;

ENERGY CONSERVATION;

EID: 0003083316     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1999.758293     Document Type: Conference Paper

References (12)

1. [l] K. K. Parhi, “Algorithmtransformationtechniques for concurrentprocessors,”Proceedingsofthe IEEE,vol.77,no. 12, pp. 1879-1895,Dec. 1989.
2. A. Chandrakasan et al., “Minimizing power using transformations,” IEEE Trans. Computer-AidedDesign, vol. 14, no. 1, pp. 12-31, Jan. 1995.
3. M. Goel and N. R. Shanbhag, “Low-power equalizers for 51.84 Mb/s very high-speed digital subscriber loop (VDSL) modems,” in Proceedings of IEEE V U 1Signal Processing Workshop,(Boston, MA), Oct. 1998.
4. M. Goel and N. R. Shanbhag, “Dynamic algorithm transformations (DAT) for low-power adaptive signal processing,”ProceedingsofInternationalSymposiumonLowPower ElectronicsandDesign,pp. 161-166, Aug. 1997.
5. A. Raghupathy and K. J. R. Liu, “Low powerhigh speed design of a Reed Solomon decoder,” in ISCAS, (Hong Kong), pp. 2060-2063, June 1997.
6. S. K. Jain, L. Song, and K. K. Parhi, “Efficient semisystolic architectures for finite-field arithmetic,” IEEE Trans. VLSI, vol. 6, no. 1,pp. 101-113.1998.
7. Y. R. Shayan and T. Le-Ngoc, “A cellular structure for a versatile Reed-Solomon decoder,” IEEE Trans. on Computers, vol. 46, no. 1, pp. 80-85, Jan. 1997.
8. W. Wilhelm, A. Kaufman, and T. G. Noll, “A new scalable VLSI architecturefor Reed-Solomondecoders,” in Proceedings, Custom Integrated Circuits Conference,(Santa Clara, California),pp. 2.3.1-2.3.4, May 1998.
9. T. Le-Ngoc, M. T. Vo, B. Mallett, and V. K.Bhargava, “A gate-amy basedprogrammableReed-Solomoncodec: Structure -implementation-applications,”in ProceedingsoflEEE CustomIntegrated Circuits Conference,pp. 121-124,1990.
10. [lo] R. E. Blahut, Theory and Practice of Error Control Codes. Reading, MA: Addison-Wesley, 1983.
11. [ I l l M. G. Xakellis and F. N. Najm, “Statistical estimation of the switching activity in digital circuits,” in Design Automation Conference,pp. 728-733, June 1994.
12. M. A. Hasan and V. K. Bhargava, “Architecture for a low-complexity rate-adaptive Reed-Solomon encoder,” IEEE Trans.on Coniputers,vol. 44, no. 7, pp. 938-942, July 1995.