Effect of back-gate biasing on the performance and leakage control in deeply scaled SOI MOSFETs

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 58-59

  Khakifirooz, Ali ^a   Antoniadis, Dimitri A ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; LEAKAGE CURRENTS; SEMICONDUCTING FILMS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

BACK-GATE BIASING;

MOSFET DEVICES;

EID: 0036905779     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044415     Document Type: Conference Paper

References (3)

1. A. Keshavarzi, et al., Int. Symp. Low Power Electronics and Designs, p. 207, 2001.
2. I. Yang, et al., IEDM, p.877, 1995.
3. D. Esseni, et al., IEDM, p. 445, 2001.