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Volumn 2003-January, Issue , 2003, Pages 223-226

Physical compact model for threshold voltage in short-channel double-gate devices

Author keywords

Back; Capacitance; Current voltage characteristics; Extrapolation; Intrusion detection; MOSFET circuits; Photonic band gap; Predictive models; Threshold voltage; Transconductance

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; ENERGY GAP; EXTRAPOLATION; FIELD EFFECT TRANSISTORS; INTRUSION DETECTION; MOS DEVICES; PHOTONIC BAND GAP; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

EID: 84943269117     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2003.1233677     Document Type: Conference Paper
Times cited : (20)

References (8)
  • 1
    • 85056911965 scopus 로고
    • Monte Carlo simulation of 30 nm dual-gate MOSFET: How short can Si go?
    • Dec.
    • D. J. Frank, S. E. Laux, and M. V. Fischetti, "Monte Carlo simulation of 30 nm dual-gate MOSFET: how short can Si go?," IEDM Tech. Dig., pp. 553-556, Dec. 1992.
    • (1992) IEDM Tech. Dig. , pp. 553-556
    • Frank, D.J.1    Laux, S.E.2    Fischetti, M.V.3
  • 4
    • 0035250378 scopus 로고    scopus 로고
    • Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
    • Feb.
    • K. Kim and J. G. Fossum, "Double-gate CMOS: symmetrical-versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol 48., pp. 294-299, Feb. 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , pp. 294-299
    • Kim, K.1    Fossum, J.G.2
  • 7
    • 0024106969 scopus 로고
    • A Physical shortchannel model for the thin-film SOI MOSFET applicable to device and circuit CAD
    • Nov.
    • S. Veeraraghavan and J. G. Fossum, "A Physical shortchannel model for the thin-film SOI MOSFET applicable to device and circuit CAD," IEEE Trans. Electron Devices, vol. 35, pp. 1866-1875, Nov. 1988.
    • (1988) IEEE Trans. Electron Devices , vol.35 , pp. 1866-1875
    • Veeraraghavan, S.1    Fossum, J.G.2
  • 8
    • 0032284102 scopus 로고    scopus 로고
    • Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25nm channel length generation
    • Dec.
    • H.-S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25nm channel length generation," IEDM Tech. Dig., pp. 407-410, Dec. 1998.
    • (1998) IEDM Tech. Dig. , pp. 407-410
    • Wong, H.-S.P.1    Frank, D.J.2    Solomon, P.M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.