Organizing the last line of defense before hitting the memory wall for CMPs

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn 10, Issue , 2004, Pages 176-185

  Liu, Chun ^a   Sivasubramaniam, Anand ^a   Kandemir, Mahmut ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS (CMP); OFF CHIP MEMORY; SYMMETRIC MULTIPROCESSORS;

CACHE MEMORY; COMPUTER OPERATING SYSTEMS; COMPUTER PROGRAMMING LANGUAGES; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; PROGRAM PROCESSORS;

MULTIPROCESSING SYSTEMS;

EID: 2342468635     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1002/0471648272.ch11     Document Type: Conference Paper

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