Wafer-level modular testing of core-based SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 10, 2007, Pages 1144-1153

  Bahukudumbi, Sudarshan ^a,b   Chakrabarty, Krishnendu ^a,b  

^a Duke University   (United States)

^b IEEE

Author keywords

Defect screening; Integer linear programming; System on chip (SoC) test; Test length selection; Wafer sort

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; CONSTRAINT THEORY; CONSUMER ELECTRONICS; COST BENEFIT ANALYSIS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; OPTIMIZATION; STATISTICAL METHODS;

DEFECT SCREENING; SYSTEM ON CHIP (SOC) TESTS; TEST LENGTH SELECTION; WAFER SORT;

MICROPROCESSOR CHIPS;

EID: 34648857553     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.903943     Document Type: Article

References (33)

1. Y. Zorian, E. Marinissen, and S. Dey, "Testing embedded core-based system chips," IEEE Comput., vol. 32, no. 6, pp. 52-60, Jun. 1999.
2. "International technology roadmap for semiconductors," 2005. [Online]. Available: http://www.itrs.net/Common/2005ITRS/Home2005.htm
3. IEEE Standard for Embedded Core Test, IEEE Standard 1500, 2004.
4. C. P. Su and C. W. Wu, "A graph-based approach to power-constrained SoC test scheduling," J. Electron. Test.: Theory Appl., vol. 19, pp. 45-60, Feb. 2004.
5. V. Iyengar, K. Chakrabarty, and E. Marinissen, "Test access mechanism optimization, test scheduling and tester data volume reduction for system-on-chip," IEEE Trans. Comput., vol. 52, no. 12, pp. 1619-1632, Dec. 2003.
6. V. Iyengar, K. Chakrabarty, and E. Marinissen, "Test wrapper and test access mechanism, co-optimization for system-on-chip," J. Electron. Test. Theory Appl., vol. 18, pp. 213-230, Apr. 2002.
7. E. Larsson, K. Arvidsson, H. Fujiwara, and Z. Peng, "Efficient test solutions for core-based designs," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 23, no. 5, pp. 758-775, May 2004.
8. Q. Xu and N. Nicolici, "Modular SoC testing with reduced wrapper count," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 12, pp. 1894-1908, Dec. 2005.
9. W. Zou, S. M. Reddy, and I. Pomeranz, "SoC test scheduling using simulated annealing," in Proc. VLSI Test Symp., 2003, pp. 325-330.
10. S. K. Goel and E. J. Marinissen, "Effective and efficient test architecture design for SOCs," in Proc. Int. Test Conf., 2002, pp. 529-538.
11. E. Larsson et al., "Defect-aware SoC test scheduling," in Proc. VLSI Test Symp., 2004, pp. 228-233.
12. U. Ingelsson et al., "Test scheduling for modular SOCs in an abort-on-fail environment," in Proc. Eur. Test Symp., 2005, pp. 8-13.
13. A. B. Kahng, "The road ahead: The significance of packaging," IEEE Des. Test, vol. 52, no. 12, pp. 1619-1632, Dec. 2003.
14. P. C. Maxwell, "Wafer-package test mix for optimal defect detection and test time savings," IEEE Des. Test Comput., vol. 20, no. 5, pp. 84-89, Sep. 2003.
15. I. Koren, Z. Koren, and C. H. Strapper, "A unified negative-binomial distribution for yield analysis of defect-tolerant circuits," IEEE Trans. Comput., vol. 42, no. 6, pp. 724-734, Jun. 1993.
16. I. Koren and C. H. Strapper, Yield Models for Defect Tolerant VLSI Circuits: A Review. New York: Plenum, 1989.
17. C. H. Strapper, "Small-area fault clusters and fault-tolerance in VLSI systems," IBM J. Res. Develop., vol. 33, pp. 174-177, Mar. 1989.
18. J. A. Cunningham, "The use and evaluation of yield models in integrated circuit manufacturing," IEEE Trans. Semicond. Manuf., vol. 3, no. 2, pp. 60-71, May 1990.
19. T. S. Barnett et al., "Combining negative binomial and weibull distributions for yield and reliability predictions," IEEE Des. Test, vol. 23, no. 2, pp. 110-116, Mar./Apr. 2006.
20. T. S. Barnett and A. D. Singh, "Relating yield models to burn-in fall-out in time," in Proc. IEEE Int. Test Conf., 2003, pp. 77-84.
21. J. T. de Sousa and V. D. Agrawal, "Reducing the complexity of defect level modeling using the clustering effect," in Proc. Des. Autom. Test Conf., 2000, pp. 640-644.
22. S. K. Goel and E. J. Marinissen, "Layout-driven. SoC test architecture design for test time and wire length, minimization," in Proc. Des. Autom. Test Conf., 2003, pp. 738-743.
23. E. J. Marinissen. et al., "A set of benchmarks for modular testing of SOCs," in Proc. IEEE Int. Test Conf., 2002, pp. 519-528. [Online]. Available: http://www.hitech-projects.com/itc02socbenchm/
24. E. Larsson and Z. Peng, "An integrated framework for the design and optimization of SoC test solutions," J. Electron. Test.: Theory Appl., vol. 18, pp. 385-400, Feb. 2002.
25. V. Iyengar and K. Chakrabarty, "Test bus sizing for system-on-a-chip," IEEE Trans. Comput., vol. 5.1, no. 5, pp. 449-459, May 2005.
26. S. Koranne, "A novel reconfigurable wrapper for testing of embedded core-based socs and its associated scheduling algorithm," J. Electron. Test.: Theory Appl., vol. 18, pp. 415-434, Aug. 2002.
27. M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Reading, MA: Kluwer, 2000.
28. E. Larsson and H. Fujiwara, "Optimal system-on-chip test scheduling," in Proc. Asian Test Symp., 2004, pp. 306-311.
29. E. Kreyszig, Advanced Engineering Mathematics, 8th ed. New York: Wiley, 1998.
30. M. Berkelaar et al., "lpsolve: Open source (mixed-integer) linear programming system, ver. 5.5," 2005. [Online], Available: http://www.geocities.com/lpsolve
31. Frontline Systems Inc., Incline Village, NV, "Premium solver platform," 2007. [Online]. Available: http://www.solver.com/xlsplat-form. html
32. M. S. Bazaraa, H. D. Sherali, and C. M. Shetty, Nonlinear Progmmming: Theory and Algorithms, 3rd ed. New York: Wiley, 2006.
33. R. Webster, Convexity, 2nd ed. London, U.K.: Oxford Sci., 1995.