Wafer-package test mix for optimal defect detection and test time savings

IEEE Design and Test of Computers

Volumn 20, Issue 5, 2003, Pages 84-89

  Maxwell, Peter C ^a  

^a AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DELAY CIRCUITS; ELECTRIC POTENTIAL; ELECTRONICS PACKAGING; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); SILICON WAFERS; STATIC RANDOM ACCESS STORAGE;

DEFECT DETECTION; FUNCTIONAL VECTORS; VENN DIAGRAMS; WAFER-PACKAGE TEST MIX;

INTEGRATED CIRCUIT TESTING;

EID: 0142071666     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1232260     Document Type: Article

References (8)

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