Defect-aware SOC test scheduling

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2004, Pages 359-364

  Larsson, Erik ^a   Pouget, Julien ^b   Peng, Zebo ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

^b LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUS STRUCTURES; ELECTRONIC SYSTEMS; SYSTEM-ON-CHIP DESIGNS; TEST SCHEDULING;

AUTOMATIC TESTING; INTERFACES (COMPUTER); OPTIMIZATION; PROBABILITY; PROBLEM SOLVING; SCHEDULING;

ELECTRONIC EQUIPMENT;

EID: 3142752834     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2004.1299265     Document Type: Conference Paper

References (13)

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