Relating Yield Models to Burn-In Fall-Out in Time

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 77-84

  Barnett, Thomas S ^a   Singh, Adit D ^b  

^a IBM MICROELECTRONICS   (United States)

^b AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FUNCTIONS; RELIABILITY; WEIBULL DISTRIBUTION;

BURN IN BOARDS (BIB);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0142184831     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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9. I. Koren, Z. Koren and C.H. Stapper, "A Unified Negative Binomial Distribution for Yield Analysis of Defect Tolerant Circuits," IEEE Trans, on Computers, Vol. 42, June 1993, pp. 724-437.
10. T.S. Barnett, A.D. Singh and V.P. Nelson, "Estimating Burn-In Fall-Out for Redundant Memory", Proceedings 2001 International Test Conference, October 2001, pp. 340-347.
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12. R. Madge, M. Rehani, K. Cota, W.R. Daasch, "Statistical Post-Processing at Wafersort: An Alternative to Burn-In and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies", Proceedings 2002 VLSI Test Symposium, May 2002, pp. 69-74.