Optimal system-on-chip test scheduling

Proceedings of the Asian Test Symposium

Volumn 2003-January, Issue , 2003, Pages 306-311

  Larsson, E ^a,b   Fujiwara, H ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; OPTIMAL SYSTEMS; SCHEDULING; SYSTEM-ON-CHIP;

IDENTICAL MACHINES; ITS EFFICIENCIES; JOB SCHEDULING; OPTIMAL SOLUTIONS; PRE-EMPTIVE SCHEDULING; RECONFIGURABLE; SYSTEM-ON-CHIP TEST; TEST ACCESS MECHANISM;

SCHEDULING ALGORITHMS;

EID: 34648833691     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250828     Document Type: Conference Paper

References (11)

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11. S. Koranne and V. Iyengar, "On the Use of k-tuples for SoC Test Schedule Representation", Proceedings of International Test Conference (ITC), pp. 539-548, October 2002.