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Volumn 23, Issue 2, 2006, Pages 110-116

Combining negative binomial and weibull distributions for yield and reliability prediction

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; DATA STRUCTURES; RELIABILITY; WEIBULL DISTRIBUTION;

EID: 33645816786     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2006.38     Document Type: Article
Times cited : (13)

References (10)
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    • H.H. Huston and C.P. Clarke, "Reliability Defect Detection and Screening during Processing - Theory and Implementation," Proc. 30th Ann. Int'l Reliability Physics Symp., IEEE Press, 1992, pp. 268-275.
    • (1992) Proc. 30th Ann. Int'l Reliability Physics Symp. , pp. 268-275
    • Huston, H.H.1    Clarke, C.P.2
  • 2
    • 0020735104 scopus 로고
    • "Integrated Circuit Yield Statistics"
    • Apr
    • C.H. Stapper, F.M. Armstrong, and K. Saji, "Integrated Circuit Yield Statistics," Proc. IEEE, vol. 71, no. 4, Apr. 1983, pp. 453-470.
    • (1983) Proc. IEEE , vol.71 , Issue.4 , pp. 453-470
    • Stapper, C.H.1    Armstrong, F.M.2    Saji, K.3
  • 3
    • 0348233291 scopus 로고    scopus 로고
    • "Extending Integrated Circuit Models to Estimate Early-Life Reliability"
    • Sept
    • T.S. Barnett, A.D. Singh, and V.P. Nelson, "Extending Integrated Circuit Models to Estimate Early-Life Reliability," IEEE Trans. Reliability, vol. 52, no. 3, Sept. 2003, pp. 296-300.
    • (2003) IEEE Trans. Reliability , vol.52 , Issue.3 , pp. 296-300
    • Barnett, T.S.1    Singh, A.D.2    Nelson, V.P.3
  • 4
    • 0032639191 scopus 로고    scopus 로고
    • "Microprocessor Reliability Performance as a Function of Die Location for a 0.25-μm Five Layer Metal CMOS Logic Process"
    • IEEE Press
    • W. Riordan et al., "Microprocessor Reliability Performance as a Function of Die Location for a 0.25-μm Five Layer Metal CMOS Logic Process," Proc. 37th Ann. Int'l Reliability Physics Symp., IEEE Press, 1999, pp. 1-11.
    • (1999) Proc. 37th Ann. Int'l Reliability Physics Symp. , pp. 1-11
    • Riordan, W.1
  • 5
    • 0035680818 scopus 로고    scopus 로고
    • "Unit Level Predicted Yield: A Method of Identifying High Defect Density Die at Wafer Sort"
    • IEEE Press
    • R. Miller and W. Riordan, "Unit Level Predicted Yield: A Method of Identifying High Defect Density Die at Wafer Sort," Proc. Int'l Test Conf. (ITC 01), IEEE Press, 2001, pp. 1118-1127.
    • (2001) Proc. Int'l Test Conf. (ITC 01) , pp. 1118-1127
    • Miller, R.1    Riordan, W.2
  • 6
    • 0010401965 scopus 로고    scopus 로고
    • "Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction"
    • IEEE Press
    • T.S. Barnett et al., "Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction," Proc. 20th VLSI Test Symp. (VTS 02), IEEE Press, 2002, pp. 75-80.
    • (2002) Proc. 20th VLSI Test Symp. (VTS 02) , pp. 75-80
    • Barnett, T.S.1
  • 7
    • 0036445139 scopus 로고    scopus 로고
    • "Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model"
    • IEEE Press
    • T.S. Barnett et al., "Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model," Proc. Int'l Test Conf. (ITC 02), IEEE Press, 2002, pp. 693-699.
    • (2002) Proc. Int'l Test Conf. (ITC 02) , pp. 693-699
    • Barnett, T.S.1
  • 8
    • 0142184831 scopus 로고    scopus 로고
    • "Relating Yield Models to Burn-in Fall-Out in Time"
    • IEEE Press
    • T.S. Barnett and A.D. Singh, "Relating Yield Models to Burn-in Fall-Out in Time," Proc. Int'l Test Conf. (ITC 03), IEEE Press, 2003, pp. 77-84.
    • (2003) Proc. Int'l Test Conf. (ITC 03) , pp. 77-84
    • Barnett, T.S.1    Singh, A.D.2
  • 10
    • 0002322314 scopus 로고
    • "Yield Models for Defect Tolerant VLSI Circuits: A Review"
    • I. Koren, ed., Plenum
    • I. Koren and C. H. Stapper, "Yield Models for Defect Tolerant VLSI Circuits: A Review," Defect and Fault Tolerance in VLSI Systems, vol. 1, I. Koren, ed., Plenum, 1989, pp. 1-21.
    • (1989) Defect and Fault Tolerance in VLSI Systems , vol.1 , pp. 1-21
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.