Parametric yield analysis and optimization in leakage dominated technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 6, 2007, Pages 613-623

  Agarwal, Kanak ^a,b   Rao, Rahul ^a,c   Sylvester, Dennis ^a,d   Brown, Richard ^a,e  

^a IEEE   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d UNIVERSITY OF MICHIGAN   (United States)

^e University of Utah   (United States)

Author keywords

Leakage; Optimal supply voltage; Optimal threshold voltage; Process variation; Yield estimation; Yield optimization

Indexed keywords

FREQUENCY CONSTRAINTS; OPTIMAL SUPPLY VOLTAGE; OPTIMAL THRESHOLD VOLTAGE; PARAMETRIC YIELD ANALYSIS; SHIPPING FREQUENCY;

CMOS INTEGRATED CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; PARAMETER ESTIMATION; THRESHOLD VOLTAGE;

NANOTECHNOLOGY;

EID: 34250203956     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.898625     Document Type: Article

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