Speed binning with path delay test in 150-nm technology

IEEE Design and Test of Computers

Volumn 20, Issue 5, 2003, Pages 41-45

  Cory, Bruce D ^a   Kapur, Rohit ^b   Underwood, Bill ^b  

^a nVidia ^*

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; FAULT TOLERANT COMPUTER SYSTEMS; NANOTECHNOLOGY;

PATH DELAY TEST; SPEED BINNING; STUCK AT FAULT MODEL; TRANSITION FAULT MODEL;

COMPUTER TESTING;

EID: 0142135003     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1232255     Document Type: Article

References (12)

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