-
3
-
-
0025476911
-
An RNS discrete Fourier transform implementation
-
Aug
-
F. J. Taylor, "An RNS discrete Fourier transform implementation," IEEE Trans. Acoust., Speech, Signal Process., vol. 38, no. 8, pp. 1386-1394, Aug. 1990.
-
(1990)
IEEE Trans. Acoust., Speech, Signal Process
, vol.38
, Issue.8
, pp. 1386-1394
-
-
Taylor, F.J.1
-
4
-
-
0029696294
-
ASAP-A 2-D DFT VLSI processor and architecture
-
J. D. Mellott, M. Lewis, F. Taylor, and P. Coffield, "ASAP-A 2-D DFT VLSI processor and architecture," in Proc. IEEE Int. Symp. Circuits Syst., 1996, vol. 2, pp. 261-264.
-
(1996)
Proc. IEEE Int. Symp. Circuits Syst
, vol.2
, pp. 261-264
-
-
Mellott, J.D.1
Lewis, M.2
Taylor, F.3
Coffield, P.4
-
5
-
-
0032637605
-
A modular approach to the computation of convolution sum using distributed arithmetic principles
-
Jan
-
K. P. Lim and A. B. Premkumar, "A modular approach to the computation of convolution sum using distributed arithmetic principles," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 1, pp. 92-96, Jan. 1999.
-
(1999)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.46
, Issue.1
, pp. 92-96
-
-
Lim, K.P.1
Premkumar, A.B.2
-
6
-
-
0034483512
-
Real-time implementation of fractal image encoder using residue number system
-
May
-
B. Rejeb, H. Henkelmann, and W. Anheier, "Real-time implementation of fractal image encoder using residue number system," in Proc. 10th Medit. Electrotech. Conf., May 2000, vol. 2, pp. 612-615.
-
(2000)
Proc. 10th Medit. Electrotech. Conf
, vol.2
, pp. 612-615
-
-
Rejeb, B.1
Henkelmann, H.2
Anheier, W.3
-
7
-
-
0027635116
-
On theory and fast algorithms for error correction in residue number system product codes
-
Jul
-
H. Krishna and J. Sun, "On theory and fast algorithms for error correction in residue number system product codes," IEEE Trans. Comput., vol. 42, no. 7, pp. 840-853, Jul. 1993.
-
(1993)
IEEE Trans. Comput
, vol.42
, Issue.7
, pp. 840-853
-
-
Krishna, H.1
Sun, J.2
-
8
-
-
0034313596
-
Adaptive redundant residue number system coded multicarrier modulation
-
Nov
-
T. Keller, T. H. Liew, and L. Hanzo, "Adaptive redundant residue number system coded multicarrier modulation," IEEE J. Sel. Areas Commun. vol. 18, no. 11, pp. 2292-2301, Nov. 2000.
-
(2000)
IEEE J. Sel. Areas Commun
, vol.18
, Issue.11
, pp. 2292-2301
-
-
Keller, T.1
Liew, T.H.2
Hanzo, L.3
-
9
-
-
34249093072
-
A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system
-
G. Alia and E. Martinelli, "A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system," Inf. Process. Lett., vol. 18, pp. 141-145, 1984.
-
(1984)
Inf. Process. Lett
, vol.18
, pp. 141-145
-
-
Alia, G.1
Martinelli, E.2
-
10
-
-
0020734592
-
A fully parallel mixed-radix conversion algorithm for residue number applications
-
Apr
-
C. H. Huang, "A fully parallel mixed-radix conversion algorithm for residue number applications," IEEE Trans. Comput., vol. C-32, no. 4, pp. 398-402, Apr. 1983.
-
(1983)
IEEE Trans. Comput
, vol.C-32
, Issue.4
, pp. 398-402
-
-
Huang, C.H.1
-
11
-
-
0024104042
-
Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa
-
Nov
-
R. M. Capocelli and R. Giancarlo, "Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 35, no. 11, pp. 1425-1430, Nov. 1988.
-
(1988)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.35
, Issue.11
, pp. 1425-1430
-
-
Capocelli, R.M.1
Giancarlo, R.2
-
12
-
-
0026852363
-
Fast and flexible architectures for RNS arithmetic decoding
-
Apr
-
K. M. Elleithy and M. A. Bayoumi, "Fast and flexible architectures for RNS arithmetic decoding," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 4, pp. 226-235, Apr. 1992.
-
(1992)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.39
, Issue.4
, pp. 226-235
-
-
Elleithy, K.M.1
Bayoumi, M.A.2
-
13
-
-
0032073932
-
Area-time-efficient VLSI residue-to-binary converters
-
May
-
T. Srikanthan, M. Bhardwaj, and C. T. Clarke, "Area-time-efficient VLSI residue-to-binary converters," Proc. IEE Comput. Digit. Tech., vol. 145, no. 3, pp. 229-235, May 1998.
-
(1998)
Proc. IEE Comput. Digit. Tech
, vol.145
, Issue.3
, pp. 229-235
-
-
Srikanthan, T.1
Bhardwaj, M.2
Clarke, C.T.3
-
14
-
-
0024104425
-
A new efficient memoryless residue to binary converter
-
Nov
-
S. Andraos and H. Ahmad, "A new efficient memoryless residue to binary converter," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 35, no. 11, pp. 1441-1444, Nov. 1988.
-
(1988)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.35
, Issue.11
, pp. 1441-1444
-
-
Andraos, S.1
Ahmad, H.2
-
15
-
-
0033905449
-
Residue-to-binary converters based on new chinese remainder theorems
-
Mar
-
Y. Wang, "Residue-to-binary converters based on new chinese remainder theorems," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 3, pp. 192-206, Mar. 2000.
-
(2000)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.47
, Issue.3
, pp. 192-206
-
-
Wang, Y.1
-
16
-
-
0029388575
-
A high speed realization of residue to binary number conversion
-
Oct
-
S. J. Piestrak, "A high speed realization of residue to binary number conversion," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 10, pp. 661-663, Oct. 1995.
-
(1995)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.42
, Issue.10
, pp. 661-663
-
-
Piestrak, S.J.1
-
17
-
-
0032000038
-
k-1 - 1)
-
Feb
-
k-1 - 1)," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 2, pp. 204-209, Feb. 1998.
-
(1998)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.45
, Issue.2
, pp. 204-209
-
-
Hiasat, A.A.1
Abdel-Aty-Zohdy, H.S.2
-
18
-
-
0032095889
-
RNS-to-binary conversion for efficient VLSI implementation
-
Jun
-
G. C. Cardarilli, M. Re, and R. Lojacono, "RNS-to-binary conversion for efficient VLSI implementation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 6, pp. 667-669, Jun. 1998.
-
(1998)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl
, vol.45
, Issue.6
, pp. 667-669
-
-
Cardarilli, G.C.1
Re, M.2
Lojacono, R.3
-
19
-
-
0032117670
-
High-speed and low-cost reverse converters for the {2n- 1,2n + 1} moduli set
-
Jul
-
A. B. Premkumar, M. Bhardwaj, and T. Srikanthan, "High-speed and low-cost reverse converters for the {2n- 1,2n + 1} moduli set," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. vol. 45, no. 7, pp. 903-908, Jul. 1998.
-
(1998)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.45
, Issue.7
, pp. 903-908
-
-
Premkumar, A.B.1
Bhardwaj, M.2
Srikanthan, T.3
-
20
-
-
0033101822
-
Implementation issues of the two-level residue number system with pairs of conjugate moduli
-
Mar
-
A. Skavantzos and M. Abdallah, "Implementation issues of the two-level residue number system with pairs of conjugate moduli," IEEE Trans. Signal Process., vol. 47, no. 3, pp. 826-838, Mar. 1999.
-
(1999)
IEEE Trans. Signal Process
, vol.47
, Issue.3
, pp. 826-838
-
-
Skavantzos, A.1
Abdallah, M.2
-
21
-
-
0032155165
-
n+1} moduli set
-
Sep
-
n+1} moduli set," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 9, pp. 998-1002, Sep. 1998.
-
(1998)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl
, vol.45
, Issue.9
, pp. 998-1002
-
-
Bhardwaj, M.1
Premkumar, A.B.2
Srikanthan, T.3
-
22
-
-
0034262666
-
An improved residue-to-binary converter
-
Sep
-
Z. Wang, G. A. Jullien, and W. C. Miller, "An improved residue-to-binary converter," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 9, pp. 1437-1440, Sep. 2000.
-
(2000)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl
, vol.47
, Issue.9
, pp. 1437-1440
-
-
Wang, Z.1
Jullien, G.A.2
Miller, W.C.3
-
23
-
-
0036648036
-
n + 1)
-
Jul
-
n + 1)," IEEE Trans. Signal Process., vol. 50, no. 7, pp. 1772-1779, Jul. 2002.
-
(2002)
IEEE Trans. Signal Process
, vol.50
, Issue.7
, pp. 1772-1779
-
-
Wang, Y.1
Song, X.2
Aboulhamid, M.3
Shen, H.4
-
24
-
-
0032633424
-
-
1 + 1, in in Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia, Apr. 1999, pp. 168-175.
-
1 + 1)," in in Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia, Apr. 1999, pp. 168-175.
-
-
-
-
25
-
-
0038070753
-
A memoryless reverse converter for the 4-moduli superset
-
Apr
-
A. P. Vinod and A. B. Premkumar, "A memoryless reverse converter for the 4-moduli superset," J. Circuits, Syst. and Comput., vol. 10, no. 1&2, pp. 85-100, Apr. 2000.
-
(2000)
J. Circuits, Syst. and Comput
, vol.10
, Issue.1-2
, pp. 85-100
-
-
Vinod, A.P.1
Premkumar, A.B.2
-
26
-
-
24944514297
-
n-1 + 1)
-
Sep
-
n-1 + 1)," Proc. IEE Comput. Digit. Tech., vol. 152, no. 5, pp. 687-696, Sep. 2005.
-
(2005)
Proc. IEE Comput. Digit. Tech
, vol.152
, Issue.5
, pp. 687-696
-
-
Cao, B.1
Srikanthan, T.2
Chang, C.H.3
-
27
-
-
4344631030
-
Design of residue-to-binary converter for a new 5-moduli superset residue number system
-
Vancouver, Canada, May
-
B. Cao, T. Srikanthan, and C. H. Chang, "Design of residue-to-binary converter for a new 5-moduli superset residue number system," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, Canada, May 2004, vol. 2, pp. 841-844.
-
(2004)
Proc. IEEE Int. Symp. Circuits Syst
, vol.2
, pp. 841-844
-
-
Cao, B.1
Srikanthan, T.2
Chang, C.H.3
-
28
-
-
0031651161
-
An efficient residue to weighted converter for a new residue number system
-
New Orleans, LA, Feb
-
A. Skavantzos, "An efficient residue to weighted converter for a new residue number system," in Proc. 8th Great Lakes Symp. VLSI, New Orleans, LA, Feb. 1998, no. 9, pp. 185-191.
-
(1998)
Proc. 8th Great Lakes Symp. VLSI
, Issue.9
, pp. 185-191
-
-
Skavantzos, A.1
-
29
-
-
0033292146
-
Fast residue-to-binary converter architectures
-
Aug
-
J. Mathew, D. Radhakrishnan, and T. Srikanthan, "Fast residue-to-binary converter architectures," in Proc. 4nd Midwest Symp. Circuits Syst. Aug. 1999, vol. 2, pp. 1090-1093.
-
(1999)
Proc. 4nd Midwest Symp. Circuits Syst
, vol.2
, pp. 1090-1093
-
-
Mathew, J.1
Radhakrishnan, D.2
Srikanthan, T.3
-
30
-
-
0142196030
-
-
2n + 1 based on the newchinese remainder theorem, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 50, no. 10, pp. 1296-1303, Oct. 2003.
-
2n + 1) based on the newchinese remainder theorem," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 10, pp. 1296-1303, Oct. 2003.
-
-
-
-
31
-
-
0032692589
-
Grouped-moduli residue number systems for fast signal processing
-
Jun
-
A. Skavantzos and T. Stouraitis, "Grouped-moduli residue number systems for fast signal processing," in Proc. Int. Symp. Circuits Syst., Jun. 1999, vol. 3, pp. 478-483.
-
(1999)
Proc. Int. Symp. Circuits Syst
, vol.3
, pp. 478-483
-
-
Skavantzos, A.1
Stouraitis, T.2
-
32
-
-
0037285243
-
Efficient residue to binary converter
-
Jan
-
A. Hiasat, "Efficient residue to binary converter," Proc. IEE Comput. Digit. Tech., vol. 150, no. 1, pp. 11-16, Jan. 2003.
-
(2003)
Proc. IEE Comput. Digit. Tech
, vol.150
, Issue.1
, pp. 11-16
-
-
Hiasat, A.1
-
34
-
-
0026907936
-
n - 1
-
Aug
-
n - 1," IEEE Trans. Comput., vol. 41, no. 8, pp. 957-961, Aug. 1992.
-
(1992)
IEEE Trans. Comput
, vol.41
, Issue.8
, pp. 957-961
-
-
Skavantzos, A.1
Rao, P.B.2
-
35
-
-
0028463884
-
n - 1 adder design
-
Jul
-
n - 1 adder design," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 41, no. 7, pp. 463-467, Jul. 1994.
-
(1994)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.41
, Issue.7
, pp. 463-467
-
-
Efstathiou, C.1
Nikolos, D.2
Kalamatianos, J.3
-
36
-
-
0032025474
-
n + 1) multiplication
-
Mar
-
n + 1) multiplication," IEEE Trans. Comput., vol. 47, no. 3, pp. 333-337, Mar. 1998.
-
(1998)
IEEE Trans. Comput
, vol.47
, Issue.3
, pp. 333-337
-
-
Ma, Y.1
-
37
-
-
0036158397
-
High-speed and reduced-area modular adder structures for RNS
-
Jan
-
A. A. Hiasat, "High-speed and reduced-area modular adder structures for RNS," IEEE Trans. Comput., vol. 51, no. 1, pp. 84-89, Jan. 2002.
-
(2002)
IEEE Trans. Comput
, vol.51
, Issue.1
, pp. 84-89
-
-
Hiasat, A.A.1
-
38
-
-
0036936883
-
n + 1 adder design
-
Dec
-
n + 1 adder design," IEEE Trans. Comput., vol. 51, no. 12, pp. 1389-1399, Dec. 2002.
-
(2002)
IEEE Trans. Comput
, vol.51
, Issue.12
, pp. 1389-1399
-
-
Vergos, H.T.1
Efstathiou, C.2
Nikolos, D.3
-
39
-
-
0027702824
-
Full adder-based arithmetic units for finite integer rings
-
Nov
-
T. Stouraitis, S. W. Kim, and A. Skavantzos, "Full adder-based arithmetic units for finite integer rings," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 40, no. 11, pp. 740-745, Nov. 1993.
-
(1993)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.40
, Issue.11
, pp. 740-745
-
-
Stouraitis, T.1
Kim, S.W.2
Skavantzos, A.3
-
40
-
-
4644238259
-
n + 1 adder
-
Sep
-
n + 1 adder," IEEE Trans. Comput., vol. 53, no. 9, pp. 1211-1216, Sep. 2004.
-
(2004)
IEEE Trans. Comput
, vol.53
, Issue.9
, pp. 1211-1216
-
-
Efstathiou, C.1
Vergos, H.T.2
Nikolos, D.3
-
41
-
-
0036158397
-
High-speed and reduced-area modular adder structures for RNS
-
Jan
-
A. A. Hiasat, "High-speed and reduced-area modular adder structures for RNS," IEEE Trans. Comput., vol. 51, no. 1, pp. 84-89, Jan. 2002.
-
(2002)
IEEE Trans. Comput
, vol.51
, Issue.1
, pp. 84-89
-
-
Hiasat, A.A.1
-
42
-
-
4544250286
-
Improved RNS FIR filter architectures
-
Jan
-
R. Conway and J. Nelson, "Improved RNS FIR filter architectures," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 1, pp. 26-28, Jan. 2004.
-
(2004)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.51
, Issue.1
, pp. 26-28
-
-
Conway, R.1
Nelson, J.2
-
43
-
-
0041672397
-
Fault-tolerant computations over replicated finite rings
-
Jul
-
L. Imbert, V. S. Dimitrov, and G. A. Jullien, "Fault-tolerant computations over replicated finite rings," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 7, pp. 858-864, Jul. 2003.
-
(2003)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl
, vol.50
, Issue.7
, pp. 858-864
-
-
Imbert, L.1
Dimitrov, V.S.2
Jullien, G.A.3
-
44
-
-
0037746718
-
A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation
-
Bangkok, Thailand, May
-
A. Garg, I. Steiner, G. A. Jullien, J. W. Haslett, and G. H. McGibney, "A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation," in Proc. IEEE Int. Symp. Circuits Syst., Bangkok, Thailand, May 2003, vol. II, pp. 157-160.
-
(2003)
Proc. IEEE Int. Symp. Circuits Syst
, vol.2
, pp. 157-160
-
-
Garg, A.1
Steiner, I.2
Jullien, G.A.3
Haslett, J.W.4
McGibney, G.H.5
-
45
-
-
0028320347
-
Design of residue generators and multioperand modular adders using carry-save adders
-
Jan
-
S. J. Piestrak, "Design of residue generators and multioperand modular adders using carry-save adders," IEEE Trans. Comput., vol. 43, pp. 68-77, Jan. 1994.
-
(1994)
IEEE Trans. Comput
, vol.43
, pp. 68-77
-
-
Piestrak, S.J.1
|