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Volumn 54, Issue 5, 2007, Pages 1041-1049

A residue-to-binary converter for a new five-moduli set

Author keywords

Mixed radix conversion (MRC); Residue arithmetic; Residue number system (RNS); Residue to binary converter; VLSI

Indexed keywords

ADDERS; ALGORITHMS; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; MATHEMATICAL TECHNIQUES; NUMBER THEORY;

EID: 34249045512     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.890623     Document Type: Article
Times cited : (92)

References (45)
  • 3
    • 0025476911 scopus 로고
    • An RNS discrete Fourier transform implementation
    • Aug
    • F. J. Taylor, "An RNS discrete Fourier transform implementation," IEEE Trans. Acoust., Speech, Signal Process., vol. 38, no. 8, pp. 1386-1394, Aug. 1990.
    • (1990) IEEE Trans. Acoust., Speech, Signal Process , vol.38 , Issue.8 , pp. 1386-1394
    • Taylor, F.J.1
  • 5
    • 0032637605 scopus 로고    scopus 로고
    • A modular approach to the computation of convolution sum using distributed arithmetic principles
    • Jan
    • K. P. Lim and A. B. Premkumar, "A modular approach to the computation of convolution sum using distributed arithmetic principles," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 1, pp. 92-96, Jan. 1999.
    • (1999) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process , vol.46 , Issue.1 , pp. 92-96
    • Lim, K.P.1    Premkumar, A.B.2
  • 6
    • 0034483512 scopus 로고    scopus 로고
    • Real-time implementation of fractal image encoder using residue number system
    • May
    • B. Rejeb, H. Henkelmann, and W. Anheier, "Real-time implementation of fractal image encoder using residue number system," in Proc. 10th Medit. Electrotech. Conf., May 2000, vol. 2, pp. 612-615.
    • (2000) Proc. 10th Medit. Electrotech. Conf , vol.2 , pp. 612-615
    • Rejeb, B.1    Henkelmann, H.2    Anheier, W.3
  • 7
    • 0027635116 scopus 로고
    • On theory and fast algorithms for error correction in residue number system product codes
    • Jul
    • H. Krishna and J. Sun, "On theory and fast algorithms for error correction in residue number system product codes," IEEE Trans. Comput., vol. 42, no. 7, pp. 840-853, Jul. 1993.
    • (1993) IEEE Trans. Comput , vol.42 , Issue.7 , pp. 840-853
    • Krishna, H.1    Sun, J.2
  • 8
    • 0034313596 scopus 로고    scopus 로고
    • Adaptive redundant residue number system coded multicarrier modulation
    • Nov
    • T. Keller, T. H. Liew, and L. Hanzo, "Adaptive redundant residue number system coded multicarrier modulation," IEEE J. Sel. Areas Commun. vol. 18, no. 11, pp. 2292-2301, Nov. 2000.
    • (2000) IEEE J. Sel. Areas Commun , vol.18 , Issue.11 , pp. 2292-2301
    • Keller, T.1    Liew, T.H.2    Hanzo, L.3
  • 9
    • 34249093072 scopus 로고
    • A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system
    • G. Alia and E. Martinelli, "A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system," Inf. Process. Lett., vol. 18, pp. 141-145, 1984.
    • (1984) Inf. Process. Lett , vol.18 , pp. 141-145
    • Alia, G.1    Martinelli, E.2
  • 10
    • 0020734592 scopus 로고
    • A fully parallel mixed-radix conversion algorithm for residue number applications
    • Apr
    • C. H. Huang, "A fully parallel mixed-radix conversion algorithm for residue number applications," IEEE Trans. Comput., vol. C-32, no. 4, pp. 398-402, Apr. 1983.
    • (1983) IEEE Trans. Comput , vol.C-32 , Issue.4 , pp. 398-402
    • Huang, C.H.1
  • 11
    • 0024104042 scopus 로고
    • Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa
    • Nov
    • R. M. Capocelli and R. Giancarlo, "Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 35, no. 11, pp. 1425-1430, Nov. 1988.
    • (1988) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process , vol.35 , Issue.11 , pp. 1425-1430
    • Capocelli, R.M.1    Giancarlo, R.2
  • 13
    • 0032073932 scopus 로고    scopus 로고
    • Area-time-efficient VLSI residue-to-binary converters
    • May
    • T. Srikanthan, M. Bhardwaj, and C. T. Clarke, "Area-time-efficient VLSI residue-to-binary converters," Proc. IEE Comput. Digit. Tech., vol. 145, no. 3, pp. 229-235, May 1998.
    • (1998) Proc. IEE Comput. Digit. Tech , vol.145 , Issue.3 , pp. 229-235
    • Srikanthan, T.1    Bhardwaj, M.2    Clarke, C.T.3
  • 15
    • 0033905449 scopus 로고    scopus 로고
    • Residue-to-binary converters based on new chinese remainder theorems
    • Mar
    • Y. Wang, "Residue-to-binary converters based on new chinese remainder theorems," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 3, pp. 192-206, Mar. 2000.
    • (2000) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process , vol.47 , Issue.3 , pp. 192-206
    • Wang, Y.1
  • 16
    • 0029388575 scopus 로고
    • A high speed realization of residue to binary number conversion
    • Oct
    • S. J. Piestrak, "A high speed realization of residue to binary number conversion," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 10, pp. 661-663, Oct. 1995.
    • (1995) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process , vol.42 , Issue.10 , pp. 661-663
    • Piestrak, S.J.1
  • 20
    • 0033101822 scopus 로고    scopus 로고
    • Implementation issues of the two-level residue number system with pairs of conjugate moduli
    • Mar
    • A. Skavantzos and M. Abdallah, "Implementation issues of the two-level residue number system with pairs of conjugate moduli," IEEE Trans. Signal Process., vol. 47, no. 3, pp. 826-838, Mar. 1999.
    • (1999) IEEE Trans. Signal Process , vol.47 , Issue.3 , pp. 826-838
    • Skavantzos, A.1    Abdallah, M.2
  • 24
    • 0032633424 scopus 로고    scopus 로고
    • 1 + 1, in in Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia, Apr. 1999, pp. 168-175.
    • 1 + 1)," in in Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia, Apr. 1999, pp. 168-175.
  • 25
    • 0038070753 scopus 로고    scopus 로고
    • A memoryless reverse converter for the 4-moduli superset
    • Apr
    • A. P. Vinod and A. B. Premkumar, "A memoryless reverse converter for the 4-moduli superset," J. Circuits, Syst. and Comput., vol. 10, no. 1&2, pp. 85-100, Apr. 2000.
    • (2000) J. Circuits, Syst. and Comput , vol.10 , Issue.1-2 , pp. 85-100
    • Vinod, A.P.1    Premkumar, A.B.2
  • 27
    • 4344631030 scopus 로고    scopus 로고
    • Design of residue-to-binary converter for a new 5-moduli superset residue number system
    • Vancouver, Canada, May
    • B. Cao, T. Srikanthan, and C. H. Chang, "Design of residue-to-binary converter for a new 5-moduli superset residue number system," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, Canada, May 2004, vol. 2, pp. 841-844.
    • (2004) Proc. IEEE Int. Symp. Circuits Syst , vol.2 , pp. 841-844
    • Cao, B.1    Srikanthan, T.2    Chang, C.H.3
  • 28
    • 0031651161 scopus 로고    scopus 로고
    • An efficient residue to weighted converter for a new residue number system
    • New Orleans, LA, Feb
    • A. Skavantzos, "An efficient residue to weighted converter for a new residue number system," in Proc. 8th Great Lakes Symp. VLSI, New Orleans, LA, Feb. 1998, no. 9, pp. 185-191.
    • (1998) Proc. 8th Great Lakes Symp. VLSI , Issue.9 , pp. 185-191
    • Skavantzos, A.1
  • 30
    • 0142196030 scopus 로고    scopus 로고
    • 2n + 1 based on the newchinese remainder theorem, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 50, no. 10, pp. 1296-1303, Oct. 2003.
    • 2n + 1) based on the newchinese remainder theorem," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 10, pp. 1296-1303, Oct. 2003.
  • 31
    • 0032692589 scopus 로고    scopus 로고
    • Grouped-moduli residue number systems for fast signal processing
    • Jun
    • A. Skavantzos and T. Stouraitis, "Grouped-moduli residue number systems for fast signal processing," in Proc. Int. Symp. Circuits Syst., Jun. 1999, vol. 3, pp. 478-483.
    • (1999) Proc. Int. Symp. Circuits Syst , vol.3 , pp. 478-483
    • Skavantzos, A.1    Stouraitis, T.2
  • 32
    • 0037285243 scopus 로고    scopus 로고
    • Efficient residue to binary converter
    • Jan
    • A. Hiasat, "Efficient residue to binary converter," Proc. IEE Comput. Digit. Tech., vol. 150, no. 1, pp. 11-16, Jan. 2003.
    • (2003) Proc. IEE Comput. Digit. Tech , vol.150 , Issue.1 , pp. 11-16
    • Hiasat, A.1
  • 36
    • 0032025474 scopus 로고    scopus 로고
    • n + 1) multiplication
    • Mar
    • n + 1) multiplication," IEEE Trans. Comput., vol. 47, no. 3, pp. 333-337, Mar. 1998.
    • (1998) IEEE Trans. Comput , vol.47 , Issue.3 , pp. 333-337
    • Ma, Y.1
  • 37
    • 0036158397 scopus 로고    scopus 로고
    • High-speed and reduced-area modular adder structures for RNS
    • Jan
    • A. A. Hiasat, "High-speed and reduced-area modular adder structures for RNS," IEEE Trans. Comput., vol. 51, no. 1, pp. 84-89, Jan. 2002.
    • (2002) IEEE Trans. Comput , vol.51 , Issue.1 , pp. 84-89
    • Hiasat, A.A.1
  • 41
    • 0036158397 scopus 로고    scopus 로고
    • High-speed and reduced-area modular adder structures for RNS
    • Jan
    • A. A. Hiasat, "High-speed and reduced-area modular adder structures for RNS," IEEE Trans. Comput., vol. 51, no. 1, pp. 84-89, Jan. 2002.
    • (2002) IEEE Trans. Comput , vol.51 , Issue.1 , pp. 84-89
    • Hiasat, A.A.1
  • 44
    • 0037746718 scopus 로고    scopus 로고
    • A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation
    • Bangkok, Thailand, May
    • A. Garg, I. Steiner, G. A. Jullien, J. W. Haslett, and G. H. McGibney, "A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation," in Proc. IEEE Int. Symp. Circuits Syst., Bangkok, Thailand, May 2003, vol. II, pp. 157-160.
    • (2003) Proc. IEEE Int. Symp. Circuits Syst , vol.2 , pp. 157-160
    • Garg, A.1    Steiner, I.2    Jullien, G.A.3    Haslett, J.W.4    McGibney, G.H.5
  • 45
    • 0028320347 scopus 로고
    • Design of residue generators and multioperand modular adders using carry-save adders
    • Jan
    • S. J. Piestrak, "Design of residue generators and multioperand modular adders using carry-save adders," IEEE Trans. Comput., vol. 43, pp. 68-77, Jan. 1994.
    • (1994) IEEE Trans. Comput , vol.43 , pp. 68-77
    • Piestrak, S.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.