Efficient reverse converters for four-moduli sets {2 n - 1, 2 n, 2 n+1, 2 n+1 - 1} and {2 n - 1, 2 n, 2 n+1, 2 n-1 - 1}

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 5, 2005, Pages 687-696

  Cao, B ^a   Srikanthan, T ^a   Chang, C H ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ADDER-BASED ARCHITECTURE; REVERSE CONVERTERS; THREE-MODULI SET;

ALGORITHMS; COMPUTER ARCHITECTURE; VLSI CIRCUITS;

PROGRAM PROCESSORS;

EID: 24944514297     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045155     Document Type: Conference Paper

References (27)

1. Szabo, N.S., and Tanaka, R.I.: 'Residue arithmetic and its applications to computer technology' (McGraw Hill Press, New York, 1967)
2. Soderstrand, M.A., Jenkins, W.K., Jullien, G.A., and Taylor, F.J.: 'Residue number system arithmetic: modern applications in digital signal processing' (IEEE Press, New York, 1986)
3. Taylor, F.J.: 'An RNS discrete Fourier transform implementation', IEEE Trans. Acoust. Speech Signal Process., 1990, 38, (8), pp. 1386-1394
4. Mellott, J.D., Lewis, M., Taylor, F.J., and Coffield, P.: 'ASAP-A 2D DFT VLSI processor and architecture'. Proc. IEEE Int. Symp. Circuits Syst., Atlanta, USA, 1996, Vol. 2, pp. 261-264
5. Lim, K.P., and Premkumar, A.B.: 'A modular approach to the computation of convolution sum using distributed arithmetic principles', IEEE Trans. Circuits Syst. II, 1999, 46, (1), pp. 92-96
6. Rejeb, B., Henkelmann, H., and Anheier, W.: 'Real-time implementation of fractal image encoder using residue number system'. Proc. 10th Mediterranean Electrotechnical Conf., Cyprus, 2000, Vol.2, pp. 612-615
7. Krishna, H., and Sun, J.D.: 'On theory and fast algorithms for error correction in residue number system product codes', IEEE Trans. Comput., 1993, 42, (7), pp. 840-853
8. Keller, T., Liew, T.H., and Hanzo, L.: 'Adaptive redundant residue number system coded multicarrier modulation', IEEE J. Sel. Areas Commun., 2000, 18, (11), pp. 2292-2301
9. Piestrak, S.J.: 'Design of residue generators and multioperand modular adders using carry-save adders', IEEE Trans. Comput., 1994, 43, (1), pp. 68-77
10. Andraos, S., and Ahmad, H.: 'A new efficient memoryless residue to binary converter', IEEE Trans. Circuits Syst., 1988, 35, (11), pp. 1441-1444
11. Piestrak, S.J.: 'A high-speed realization of a residue to binary number system converter', IEEE Trans. Circuits Syst. II, 1995, 42, (10), pp. 661-663
12. k-1 - 1)', IEEE Trans. Circuits Syst. II, 1998, 45, (2), pp. 204-209
13. 2n+l} based on the New Chinese Remainder Theorem', IEEE Trans. Circuits Syst. I, 2003, 50, (10), pp. 1296-1303
14. Skavantzos, A., and Abdallah, M.: 'Implementation issues of the two-level residue number system with pairs of conjugate moduli', IEEE Trans. Signal Process., 1999, 47, (3), pp. 826-838
15. Wang, Z., Jullien, G.A., and Miller, W.C.: 'An improved residue-to-binary converter', IEEE Trans. Circuits Syst. I, 2000, 47, (9), pp. 1437-1440
16. n+1)', IEEE Trans. Signal Process., 2002, 50, (7), pp. 1772-1779
17. n+1+1}'. Proc. 14th IEEE Symp. on Computer Arithmetic, Adelaide, Australia, 1999, pp. 168-175
18. n+1 - 1}', J. Circuits Syst. Comput., 2000, 10, (1,2), pp. 85-99
19. Skavantzos, A.: 'An efficient residue to weighted converter for a new residue number system'. Proc. 8th Great Lakes Symp. VLSI, Lafayette, LA USA, 1998, pp. 185-191
20. n+1} moduli set', IEEE Trans. Circuits Syst. I, 1998, 45, (9), pp. 998-1002
21. Skavantzos, M., and Stouraitis, T.: 'Grouped-moduli residue number systems for fast signal processing'. Proc. IEEE Int. Symp. on Circuits Syst., Orlando, FL USA, 1999, Vol. 3, pp. 478-483
22. Conway, R., and Nelson, J.: 'New CRT-based RNS converter using restricted moduli sets', IEEE Trans. Comput., 2003, 52, (5), pp. 572-578
23. Wang, Y.: 'Residue-to-binary converters based on New Chinese remainder theorems', IEEE Trans. Circuits Syst. -II, 2000, 47, (3), pp. 197-206
24. Wang, Y.: 'New Chinese remainder theorems'. Proc. 32nd Asilomar Conf. on Signals, Systems & Computers, Pacific Grove, CA USA, 1998, Vol.1, (1), pp. 165-171
25. Hwang, K.: 'Computer arithmetic: principle, architecture and deign' (Wiley Press, New York, 1979)
26. Bayoumi, M., Jullien, G., and Miller, W.C.: 'A VLSI implementation of residue adders', IEEE Trans. Circuits Syst., 1987, 34, (3), pp. 284-288
27. n - 1 adder design', IEEE Trans. Circuits Syst.-II, 1994, 41, (7), pp. 463-467