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Volumn 47, Issue 3, 1998, Pages 333-337

A simplified architecture for modulo (2n + 1) multiplication

Author keywords

Booth's algorithm; Carry lookahead adder; Carry save adder; Convolution; CSA array; Fermat number transform; Modulo (2n + 1) multiplication; RNS arithmetic; Wallace tree

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; CONVOLUTIONAL CODES; LOGIC CIRCUITS; MATHEMATICAL TRANSFORMATIONS; TREES (MATHEMATICS);

EID: 0032025474     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.660169     Document Type: Article
Times cited : (70)

References (16)
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  • 2
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  • 3
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  • 9
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  • 10
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    • Novel Approaches to the Design of VLSI RNS multipliers
    • Jan.
    • D. Radhakrishnan and Y. Yuan, "Novel Approaches to the Design of VLSI RNS multipliers," IEEE Trans. Circuits and Systems Part II, vol. 39, no. 1, pp. 52-57, Jan. 1992.
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  • 11
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  • 13
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  • 14
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.