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Volumn 45, Issue 1, 1998, Pages 204-209

Residue-to-binary arithmetic converter for the moduli set (2k, 2k - 1, 2k-1 - 1)

Author keywords

Binary numbers; Hardware implementation; Residue number system; Residue to binary conversion

Indexed keywords

ADDERS; ALGORITHMS; BINARY SEQUENCES; COMPUTATIONAL COMPLEXITY; NUMBER THEORY; PIPELINE PROCESSING SYSTEMS; SET THEORY;

EID: 0032000038     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.661651     Document Type: Article
Times cited : (94)

References (23)
  • 4
    • 0021691117 scopus 로고    scopus 로고
    • A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system,"
    • 31, pp. 1033-1039, Dec. 1984.
    • G. Alia and E. Martinelli A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system," IEEE Trans. Circuits Syst., vol. CAS-31, pp. 1033-1039, Dec. 1984.
    • IEEE Trans. Circuits Syst., Vol. CAS
    • Alia, G.1    Martinelli, E.2
  • 5
    • 0022088799 scopus 로고    scopus 로고
    • Efficient implementations of Chinese remainder theorem for sign detection and residue decoding,"
    • 34, pp. 646-651, July 1985.
    • T. Van Vu Efficient implementations of Chinese remainder theorem for sign detection and residue decoding," IEEE Trans. Comput., vol. C-34, pp. 646-651, July 1985.
    • IEEE Trans. Comput., Vol. C
    • Van Vu, T.1
  • 6
    • 0024070868 scopus 로고    scopus 로고
    • Residue to binary conversion for RNS arithmetic using only modular look-up tables,"
    • vol. 35, pp. 1158-1162, Sept. 1988.
    • A. Shenoy and R. Kumaresan Residue to binary conversion for RNS arithmetic using only modular look-up tables," IEEE Trans. Circuits Syst., vol. 35, pp. 1158-1162, Sept. 1988.
    • IEEE Trans. Circuits Syst.
    • Shenoy, A.1    Kumaresan, R.2
  • 7
    • 0024104042 scopus 로고    scopus 로고
    • Efficient VLSI networks for converting an integer from binary system and vice versa,"
    • vol. 35, pp. 1425-1430, Nov. 1988.
    • R. Capocelli and R. Giancarlo Efficient VLSI networks for converting an integer from binary system and vice versa," IEEE Trans. Circuits Syst., vol. 35, pp. 1425-1430, Nov. 1988.
    • IEEE Trans. Circuits Syst.
    • Capocelli, R.1    Giancarlo, R.2
  • 8
    • 0025503332 scopus 로고    scopus 로고
    • VLSI binary-residue converters for pipeline processing,"
    • vol. 33, no. 5, pp. 473175, 1990.
    • G. Alia and E. Martinelli VLSI binary-residue converters for pipeline processing," Computer J., vol. 33, no. 5, pp. 473175, 1990.
    • Computer J.
    • Alia, G.1    Martinelli, E.2
  • 9
    • 0026852363 scopus 로고    scopus 로고
    • Fast and flexible architectures for RNS arithmetic decoding,"
    • vol. 39, pp. 226-235, Apr. 1992
    • K. Elleithy and M. Bayoumi Fast and flexible architectures for RNS arithmetic decoding," IEEE Trans. Circuits Syst. II, vol. 39, pp. 226-235, Apr. 1992
    • IEEE Trans. Circuits Syst. II
    • Elleithy, K.1    Bayoumi, M.2
  • 11
    • 0022025270 scopus 로고    scopus 로고
    • Fast memoryless, over 64 bits, residue to decimal converter,"
    • 32, pp. 298-300, Mar. 1985.
    • B. Bernardson Fast memoryless, over 64 bits, residue to decimal converter," IEEE Trans. Circuits Syst., vol. CAS-32, pp. 298-300, Mar. 1985.
    • IEEE Trans. Circuits Syst., Vol. CAS
    • Bernardson, B.1
  • 12
    • 0024070952 scopus 로고    scopus 로고
    • An efficient residue to binary converter design,"
    • vol. 35, pp. 1156-1158, Sept. 1988.
    • K. Ibrahim and S. Saloum An efficient residue to binary converter design," IEEE Trans. Circuits Syst., vol. 35, pp. 1156-1158, Sept. 1988.
    • IEEE Trans. Circuits Syst.
    • Ibrahim, K.1    Saloum, S.2
  • 13
    • 0024104425 scopus 로고    scopus 로고
    • New efficient memoryless residue to binary converter,"
    • vol. 35, pp. 1441-1444, Nov. 1988.
    • A. Sweidan and A. Hiasat New efficient memoryless residue to binary converter," IEEE Trans. Circuits Syst., vol. 35, pp. 1441-1444, Nov. 1988.
    • IEEE Trans. Circuits Syst.
    • Sweidan, A.1    Hiasat, A.2
  • 14
    • 0028751974 scopus 로고    scopus 로고
    • Fast conversion techniques for binary-residue number system,"
    • vol. 41, pp. 927-929, Dec. 1994.
    • B. Vinnakota and V. B. Rao Fast conversion techniques for binary-residue number system," IEEE Trans. Circuits Syst., vol. 41, pp. 927-929, Dec. 1994.
    • IEEE Trans. Circuits Syst.
    • Vinnakota, B.1    Rao, V.B.2
  • 15
    • 0029292258 scopus 로고    scopus 로고
    • An RNS to binary converter in three moduli set with common factors,"
    • vol. 42, pp. 298-301, Apr. 1995.
    • A. B. Premkumar An RNS to binary converter in three moduli set with common factors," IEEE Trans. Circuits Syst. II, vol. 42, pp. 298-301, Apr. 1995.
    • IEEE Trans. Circuits Syst. II
    • Premkumar, A.B.1
  • 16
    • 0018331351 scopus 로고    scopus 로고
    • Recent advances in residue number techniques for recursive digital filters,"
    • 27, pp. 19-30, Jan. 1979.
    • W. K. Jenkins Recent advances in residue number techniques for recursive digital filters," IEEE Trans. Acoust. Speech, Signal Processing, vol. ASSP-27, pp. 19-30, Jan. 1979.
    • IEEE Trans. Acoust. Speech, Signal Processing, Vol. ASSP
    • Jenkins, W.K.1
  • 17
    • 0019592222 scopus 로고    scopus 로고
    • Large moduli multipliers for signal processing,"
    • 28, pp. 731-736, July 1981.
    • F. Taylor Large moduli multipliers for signal processing," IEEE Trans Comput., vol. C-28, pp. 731-736, July 1981.
    • IEEE Trans Comput., Vol. C
    • Taylor, F.1
  • 19
    • 0028320347 scopus 로고    scopus 로고
    • Design of residue generators and multioperand modular adders using carry-save adders,"
    • vol. 43, pp. 68-77, Jan. 1994.
    • S. Piestrak Design of residue generators and multioperand modular adders using carry-save adders," IEEE Trans. Comput., vol. 43, pp. 68-77, Jan. 1994.
    • IEEE Trans. Comput.
    • Piestrak, S.1
  • 21
    • 0028756995 scopus 로고    scopus 로고
    • Design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip," in
    • vol. 1, Lafayette, LA, Aug. 1994, pp. 42831.
    • A. Hiasat and H. Abdel-Aty-Zohdy Design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip," in Proc. IEEE MidWest Symp. Circuits Syst., vol. 1, Lafayette, LA, Aug. 1994, pp. 42831.
    • Proc. IEEE MidWest Symp. Circuits Syst.
    • Hiasat, A.1    Abdel-Aty-Zohdy, H.2
  • 22
    • 0029200295 scopus 로고    scopus 로고
    • High-speed division algorithm for residue number system," in
    • vol. 3, Seattle, WA, May 1995, pp. 1996-1999.
    • High-speed division algorithm for residue number system," in Proc. IEEE Int. Symp. Circuits Syst., vol. 3, Seattle, WA, May 1995, pp. 1996-1999.
    • Proc. IEEE Int. Symp. Circuits Syst.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.