An Efficient Reverse Converter for the 4-Moduli Set {2n - 1, 2n, 2n + 1, 22n + 1} Based on the New Chinese Remainder Theorem

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 10, 2003, Pages 1296-1303

  Cao, Bin ^a   Chang, Chip Hong ^b   Srikanthan, Thambipillai ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

New Chinese remainder theorem (CRT); Residue arithmetic; Residue number system (RNS); Residue to binary converter

Indexed keywords

DIGITAL SIGNAL PROCESSING; THEOREM PROVING; VLSI CIRCUITS;

RESIDUE ARITHMETIC;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0142196030     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.817789     Document Type: Article

References (24)

1. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and its Applications to Computer Technology. New York: McGraw-Hill, 1967.
2. M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. New York: IEEE Press, 1986.
3. S. Perumal and R. E. Siferd, "Pipelined 50 MHz CMOS ASIC for 32-bit binary to residue conversion and residue-to-binary conversion," in Proc. 7th Annual IEEE Int. ASIC Conf. And Exhibit, Rochester, NY, Sept. 1994, pp. 454-457.
4. T. Srikanthan, M. Bhardwaj, and C. T. Clarke, "Area-time-efficient VLSI residue-to-binary converters," Proc. Inst. Elect. Eng. Comput. Digit. Tech., vol. 145, no. 3, pp. 229-235, 1998.
5. S. R. Barraclough et al., "The design and implementation of the IMS A110 image and signal processor," in Proc. IEEE Custom Integr. Circuits Conf., 1989, pp. 24.5.1-24.5.4.
6. S. J. Piestrak, "Design of residue generators and multioperand modular adders using carry-save adders," IEEE Trans. Comput., vol. 43, pp. 68-77, Jan. 1994.
7. G. Alia and E. Martinelli, "A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system," IEEE Trans. Circuits Syst., vol. CAS-31, pp. 1033-1039, Dec. 1984.
8. R. M. Capocelli and R. Giancarlo, "Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa," IEEE Trans. Circuits Syst., vol. 35, pp. 1425-1430, Nov. 1988.
9. K. M. Elleithy and M. A. Bayoumi, "Fast and flexible architectures for RNS arithmetic decoding," IEEE Trans. Circuits Syst. II, vol. 39, pp. 226-235, Apr. 1992.
10. F. Barsi and M. C. Pinotti, "A fully parallel algorithm for residue-to-binary conversion," in Proc. Information Lett., vol. 50, 1994, pp. 1-8.
11. C. H. Huang, "A fully parallel mixed-radix conversion algorithm for residue number applications," IEEE Trans. Comput., vol. 32, pp. 398-402, Apr. 1983.
12. H. M. Yassine and W. R Moore, "Improved mixed-radix conversion for residue number system architectures," in Proc. Inst. Elect. Eng. -G, vol. 138, 1991, pp. 120-124.
13. S. Andraos and H. Ahmad, "A new efficient memoryless residue-to-binary converter," IEEE Trans. Circuits Syst., vol. 35, pp. 1441-1444, Nov. 1988.
14. S. J. Piestrak, "A high-speed realization of a residue-to-binary number system converter," IEEE Trans. Circuits Syst. II, vol. 42, pp., 661-663, Oct. 1995.
15. Y. Wang, "New Chinese remainder theorems," in Proc. 32th Asilomar Conf. Signals, Systems, Computers, vol. 1, 1998, pp. 165-171.
16. _, "Residue-to-binary converters based on new Chinese Remainder Theorems," IEEE Trans. Circuits Syst. II, vol. 47, pp. 197-205, Mar. 2000.
17. n + 1)," IEEE Trans. Signal Processing, vol. 50, pp. 1772-1779, July 2002.
18. n+1 + 1}," in Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia, Apr. 1999, pp. 168-175.
19. n+1 - 1}," J. Circuits, Syst., Comput., vol. 10, no. 1&2, pp. 85-99, 2000.
20. N. Robbins, Beginning Number Theory. Dubuque, IA: William. C. Brown, 1993.
21. n +1} moduli set," IEEE Trans. Circuits Syst. I, vol. 45, pp. 998-1002, Sept. 1998.
22. I. S. Reed et al., "VLSI implementation of GSC architecture with a new ripple carry adder," in Proc. ICCD'88, 1988, pp. 520-523.
23. K. Hwang, Computer Arithmetic: Principle, Architecture and Design. New York: Wiley, 1979.
24. S. J. Piestrak, "Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem," in Proc. 94th Int. Conf. Computer Design, Oct. 1994, pp. 508-511.