Area-time-efficient VLSI residue-to-binary converters

IEE Proceedings: Computers and Digital Techniques

Volumn 145, Issue 3, 1998, Pages 229-235

  Srikanthan, T ^a   Bhardwaj, M ^a   Ciarke, C T ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Multiply acciinnilatc converter; Residue comcrtcr; VLSI

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT MANUFACTURE; VLSI CIRCUITS;

COMPRESSED MULTIPLY ACCUMULATE (CMAC) CONVERTERS; RESIDUE NUMBER SYSTEMS (RNS);

CODE CONVERTERS;

EID: 0032073932     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19981948     Document Type: Article

References (14)

1. SZABO, N.S., and TANAKA, R.I.: 'Residue arithmetic and its applications to computer technology' (McGraw Hill, New York, 1967)
2. SODERSTRAND, M.A., JENKINS, W.K., JULLIEN, O.A., and TAYLOR, F.J. (Eds.):'Residue number system arithmetic : Modern applications in digital system processing' (IEEE Press, New York, 1986)
3. BAYOUMI, M.A., JULLIEN, G.A., and MILLER, W.C.: 'A look-up table VLSI design methodology for RNS structures used in DSP applications', IEEE Trans., 1987, CAS-34, (6), pp. 604-615
4. PERUMAL, S., and SIFERD, R.E.: 'Pipelined 50 MHz CMOS ASIC for 32-bit binary to residue conversion and residue to binary conversion'. Proceedings of seventh annual IEEE international conference on ASIC, 1994, pp. 454-457
5. BARSI, F., and PINOTTI, M.C.: 'A fully parallel algorithm for residue to binary conversion', Inf. Process. Lett., 1994, 50, pp. 18
6. ALIA, G., and MARTINELLI, E.: 'A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system', IEEE Trans., 1984, CAS-31, pp. 1033-1039 -j
7. CAPOCELLi; R.M., and CARLO, R.G.: 'Efficient VLSI networks for converting an integer from binary system to residue number systênvand vice-versa', IEEE Trims., 1988, CAS-35, pp. 1425-1430.:
8. ELLEITHY, K.M., and BAYOUMI, M.A.: 'Fast and flexible architectures for RNS arithmetic decoding', IEEE Trans., 1992, CAS-39, (4),' pp,'226-23
9. SHANBHAG, N.R., and SIFERD, R.E.: 'A single chip pipelined 2-D FIR filter using residue arithmetic', IEEE J. Solid-State Circuits, 1991, 26, (5), pp. 796-805
10. HUANG, C.H.: 'A fully parallel mixed radix conversion algorithm for RN applications', IEEE Trans., 1983, C-32, pp. 398-402
11. CHAKRABORTI, N.B., SOUNDARARAJAN, J.S., and REDDY, A.L.N.: 'An implementation of mixed-radix conversion for residue number applications', IEEE Trans., 1986, C-35, (8), pp. 762-764
12. KOC, C.K.: 'A fast algorithm for mixed radix conversion in residue arithmetic'. Proceedings of IEEE international conference on Computer design (ICCD), 1989, pp. 18-21
13. PIESTRAK, S.J.: 'Design of residue generators and multioperand modular adders using carry save adders', IEEE Trans., 1994, C423, (1), pp. 68-77
14. DEODHAR, A.A.: 'Residue arithmetic based correlator system design'. Thesis, School of Applied Science, Nanyang Technological University, 1996