High-speed and reduced-area modular adder structures for RNS

IEEE Transactions on Computers

Volumn 51, Issue 1, 2002, Pages 84-89

  Hiasat, Ahmad A ^a,b  

^a IEEE   (Jordan)

^b PRINCESS SUMAYA UNIVERSITY FOR TECHNOLOGY   (Jordan)

Author keywords

Carry lookahead adder; Computer arithmetic; Hardware requirements; Modular adder; Residue number system; Time delay; VLSI

Indexed keywords

BINARY CONVERTERS; CARRY-LOOKAHEAD BINARY ADDERS; MODULAR ADDER; MODULAR MULTIPLIERS; RESIDUE NUMBER SYSTEM;

COMPUTER HARDWARE; DELAY CIRCUITS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MULTIPLYING CIRCUITS; ONLINE SYSTEMS; VLSI CIRCUITS;

ADDERS;

EID: 0036158397     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.980018     Document Type: Article

References (26)

1. Fast combinatorial RNS processors for DSP applications
2. A VLSI modulo m multiplier
3. A systolic architecture for modulo multiplication
4. New efficient structure for a modular multiplier for RNS
5. A new technique for fast number comparison in residue number system
6. Design of residue generators and multioperand modular adders using carry-save adders
7. An RNS to binary converter in a three moduli set with common factors
8. A signed-digit architecture for residue to binary transformation
9. k-1 - 1)
10. Multifunction architectures for RNS processors
11. Residue-to-binary converters based on new Chinese remainder theorems
12. A single modulus complex ALU for signal processing
13. A novel implementation method for addition and subtraction in residue number systems
14. n + 1) arithmetic logic
15. A new hardware implementation of modulo adders for residue number systems
16. A VLSI implementation of residue adders
17. VLSI implementation of residue adders based on binary adders
18. Design of high-speed residue-to-binary number system converter based on Chinese remainder theorem
19. n + 1)
20. n + 1 multiplier
21. n + 1) multiplication
22. n ± 1) addition and multiplication