-
2
-
-
0004033078
-
-
Boca Raton, FL: CRC , 1994.
-
H. Krishna, B. Krishna, K. Y. Lin, and J. D. Sun, Computational Number Theory and Digital Signal Processing: Fast Algorithms and Error Control Techniques. Boca Raton, FL: CRC , 1994.
-
Computational Number Theory and Digital Signal Processing: Fast Algorithms and Error Control Techniques.
-
-
Krishna, H.1
Krishna, B.2
Lin, K.Y.3
Sun D, J.4
-
3
-
-
0028528667
-
"Rings, fields, the Chinese remainder theorem and an extension-Part I: Theory,"
-
vol. 41, pp. 641-655, Oct. 1994.
-
K. Y. Lin, B. Krishna, and H. Krishna, "Rings, fields, the Chinese remainder theorem and an extension-Part I: Theory," IEEE Trans. Circuits Syst. II, vol. 41, pp. 641-655, Oct. 1994.
-
IEEE Trans. Circuits Syst. II
-
-
Lin, K.Y.1
Krishna, B.2
Krishna, H.3
-
4
-
-
0022811668
-
"Log depth circuits for division and related problems,"
-
vol. 15, pp. 994-1003, 1986.
-
P. W. Beame, S. A. Cook, and H. J. Hoover, "Log depth circuits for division and related problems," SIAMJ. Comput., vol. 15, pp. 994-1003, 1986.
-
SIAMJ. Comput.
-
-
Beame, P.W.1
Cook, S.A.2
Hoover, H.J.3
-
5
-
-
0003819663
-
-
San Mateo, CA: Morgan Kaufmann, 1992.
-
T. Leighton, Introduction to Parallel Algorithms and Architectures: Array, Trees, Hypercubes. San Mateo, CA: Morgan Kaufmann, 1992.
-
Introduction to Parallel Algorithms and Architectures: Array, Trees, Hypercubes.
-
-
Leighton, T.1
-
6
-
-
0017930809
-
"A method for obtaining digital signatures and public-key cryptoSystems,"
-
pp. 120-126, 1978.
-
R. Rivest, A. Shamir, and L. Adleman, "A method for obtaining digital signatures and public-key cryptoSystems," Commun. ACM, pp. 120-126, 1978.
-
Commun. ACM
-
-
Rivest, R.1
Shamir, A.2
Adleman, L.3
-
8
-
-
0016357682
-
"On the use of residue arithmetic for computation,"
-
vol. C-21, pp. 1315-1317, Dec. 1974.
-
D. K. Banerji, "On the use of residue arithmetic for computation," IEEE Trans. Comput., vol. C-21, pp. 1315-1317, Dec. 1974.
-
IEEE Trans. Comput.
-
-
Banerji, D.K.1
-
11
-
-
0021428663
-
"Residue arithmetic: A tutorial with examples,"
-
vol. C-17, pp. 50-62, May 1984.
-
F. J. Taylor, "Residue arithmetic: A tutorial with examples," IEEE Comput., vol. C-17, pp. 50-62, May 1984.
-
IEEE Comput.
-
-
Taylor, F.J.1
-
12
-
-
0003597645
-
-
New York: IEEE Press, 1986.
-
M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Signal Processing. New York: IEEE Press, 1986.
-
Residue Number System Arithmetic: Modern Applications in Signal Processing.
-
-
Soderstrand, M.A.1
Jenkins, W.K.2
Jullien, G.A.3
Taylor, F.J.4
-
13
-
-
0027595025
-
"A new technique for fast number comparison in the residue number systems,"
-
vol. 42, pp. 608-612, May 1993.
-
G. Dimauro, S. Impdedovo, and G. Pirlo, "A new technique for fast number comparison in the residue number systems," IEEE Trans. Comput., vol. 42, pp. 608-612, May 1993.
-
IEEE Trans. Comput.
-
-
Dimauro, G.1
Impdedovo, S.2
Pirlo, G.3
-
14
-
-
0026910214
-
"A novel division algorithm for the residue number system,"
-
vol. 41, pp. 1026-1032, Aug. 1992.
-
M. Lu and J. Chiang, "A novel division algorithm for the residue number system," IEEE Trans. Comput., vol. 41, pp. 1026-1032, Aug. 1992.
-
IEEE Trans. Comput.
-
-
Lu, M.1
Chiang, J.2
-
15
-
-
0006433627
-
"Near-optimal residue to binary converter for the moduli,"
-
Lafayette, LA, Feb. 1998.
-
Y Wang, X.Song, and M. Aboulhamid, "Near-optimal residue to binary converter for the moduli," presented at the 8th Great Lakes Symp. VLSI, Lafayette, LA, Feb. 1998.
-
8th Great Lakes Symp. VLSI
-
-
Wang, Y.1
Song, X.2
Aboulhamid, M.3
-
16
-
-
33749877372
-
"Three number moduli sets based residue number systems,"
-
Monterey, CA, May 31-June 3 1998.
-
Y Wang, M. N. Swamy, and O. Ahmad, "Three number moduli sets based residue number systems," presented at the 1998 IEEE Int. Symp. Circuits and Systems, Monterey, CA, May 31-June 3 1998.
-
1998 IEEE Int. Symp. Circuits and Systems
-
-
Wang, Y.1
Swamy, M.N.2
Ahmad, O.3
-
17
-
-
0031366924
-
"A signed-digit architecture for residue to binary transformation,"
-
vol. 46, pp. 1146-1150, Oct. 1997.
-
F. Pourbigharaz and H. Yassine, "A signed-digit architecture for residue to binary transformation," IEEE Trans. Comput., vol. 46, pp. 1146-1150, Oct. 1997.
-
IEEE Trans. Comput.
-
-
Pourbigharaz, F.1
Yassine, H.2
-
18
-
-
0030867153
-
"The digital parallel method for fast RNS to weighted number system conversion for specific moduli,"
-
vol. 44, pp. 53-57, Jan. 1997.
-
D. Gallaher, F. Petry, and P. Srinivasan, "The digital parallel method for fast RNS to weighted number system conversion for specific moduli," IEEE Trans. Circuits Syst. II, vol. 44, pp. 53-57, Jan. 1997.
-
IEEE Trans. Circuits Syst. II
-
-
Gallaher, D.1
Petry, F.2
Srinivasan, P.3
-
19
-
-
0030400238
-
"A new algorithm for RNS decoding,"
-
vol. 43, pp. 998-1001, Dec. 1996.
-
Y Wang and M. Abd-el-barr, "A new algorithm for RNS decoding," IEEE Trans. Circuits Syst. I, vol. 43, pp. 998-1001, Dec. 1996.
-
IEEE Trans. Circuits Syst. I
-
-
Wang, Y.1
Abd-el-barr, M.2
-
20
-
-
0029388575
-
"A high-speed realization of a residue to binary number system converter,"
-
vol. 42, pp. 661-663, Oct. 1995.
-
S. Piestrak, "A high-speed realization of a residue to binary number system converter," IEEE Trans. Circuits Syst. II, vol. 42, pp. 661-663, Oct. 1995.
-
IEEE Trans. Circuits Syst. II
-
-
Piestrak, S.1
-
21
-
-
0029292258
-
"An RNS to binary converter in a three moduli set with common factors,"
-
vol. 42, pp. 298-301, Apr. 1995.
-
A. Premkumar, "An RNS to binary converter in a three moduli set with common factors," IEEE Trans. Circuits Syst. II, vol. 42, pp. 298-301, Apr. 1995.
-
IEEE Trans. Circuits Syst. II
-
-
Premkumar, A.1
-
22
-
-
0028751974
-
"Fast conversion techniques for binary-residue number systems,"
-
vol. 41, pp. 927-929, Dec. 1994.
-
B. Vinnakota and V V Rao, "Fast conversion techniques for binary-residue number systems," IEEE Trans. Circuits Syst. I, vol. 41, pp. 927-929, Dec. 1994.
-
IEEE Trans. Circuits Syst. I
-
-
Vinnakota, B.1
Rao, V.V.2
-
23
-
-
0028768239
-
"A fully parallel algorithm for residue to binary conversion,"
-
pp. 1-8, 1994.
-
F. Barsi and M. Pinotti, "A fully parallel algorithm for residue to binary conversion," IPL, pp. 1-8, 1994.
-
IPL
-
-
Barsi, F.1
Pinotti, M.2
-
24
-
-
0027646103
-
"On the lower bound to the VLSI complexity of number conversion from weighted to residue representation,"
-
vol. 42, pp. 962-967, 1993.
-
G. Alia and E. Martinelli, "On the lower bound to the VLSI complexity of number conversion from weighted to residue representation," IEEE Trans. Comput., vol. 42, pp. 962-967, 1993.
-
IEEE Trans. Comput.
-
-
Alia, G.1
Martinelli, E.2
-
25
-
-
15844399684
-
"An efficient algorithm and parallel implementations for binary and residue number systems,"
-
vol. 15, pp. 451-462, 1993.
-
C. N. Zhang, B. Shirazi, and D. Yun, "An efficient algorithm and parallel implementations for binary and residue number systems," J. Symbolic Computation, vol. 15, pp. 451-462, 1993.
-
J. Symbolic Computation
-
-
Zhang, C.N.1
Shirazi, B.2
Yun, D.3
-
26
-
-
33749883130
-
"An RNS to binary converter in 2ra + 1, 2ra, 2ra -1 moduli set,"
-
vol. 39, pp. 480182, 1992.
-
A. Premkumar, "An RNS to binary converter in 2ra + 1, 2ra, 2ra -1 moduli set," IEEE Trans. Circuits Syst., vol. 39, pp. 480182, 1992.
-
IEEE Trans. Circuits Syst.
-
-
Premkumar, A.1
-
27
-
-
0026852363
-
"Fast and flexible architectures for RNS arithmetic decoding,"
-
vol. 39, pp. 226-235, Apr. 1992.
-
K. Elleithy and M. Bayoumi, "Fast and flexible architectures for RNS arithmetic decoding," IEEE Trans. Circuits Syst., vol. 39, pp. 226-235, Apr. 1992.
-
IEEE Trans. Circuits Syst.
-
-
Elleithy, K.1
Bayoumi, M.2
-
28
-
-
0026128893
-
"Efficient residue-to-binary conversion technique with rounding error compensation,"
-
vol. 38, pp. 315-317, Mar. 1991.
-
J. Kim, K. Park, and H. Lee, "Efficient residue-to-binary conversion technique with rounding error compensation," IEEE Trans. Circuits Syst., vol. 38, pp. 315-317, Mar. 1991.
-
IEEE Trans. Circuits Syst.
-
-
Kim, J.1
Park, K.2
Lee, H.3
-
29
-
-
0025446889
-
"An universal input and output RNS converter,"
-
vol. 37, pp. 799-803, 1990.
-
S. Meehan, S. O'neil, and J. Vaccaro, "An universal input and output RNS converter," IEEE Trans. Circuits Syst., vol. 37, pp. 799-803, 1990.
-
IEEE Trans. Circuits Syst.
-
-
Meehan, S.1
O'Neil, S.2
Vaccaro, J.3
-
30
-
-
0025503332
-
"VLSI binary-to-residue converters for pipelined processing,"
-
vol. 33, no. 5, pp. 473-475, 1990.
-
G. Alia and E. Martinelli, "VLSI binary-to-residue converters for pipelined processing," The Comput. ]., vol. 33, no. 5, pp. 473-475, 1990.
-
The Comput. .
-
-
Alia, G.1
Martinelli, E.2
-
32
-
-
0024070868
-
"Residue to binary conversion for RNS arithmetic using only modular look-up tables,"
-
vol. 35, pp. 1158-1162, Sept. 1988.
-
A. Shenoy and R. Kumaresan, "Residue to binary conversion for RNS arithmetic using only modular look-up tables," IEEE Trans. Circuits Syst., vol. 35, pp. 1158-1162, Sept. 1988.
-
IEEE Trans. Circuits Syst.
-
-
Shenoy, A.1
Kumaresan, R.2
-
33
-
-
0024070952
-
"An efficient residue to binary converter design,"
-
vol. 35, pp. 1156-1158, Sept. 1988.
-
K. Ibrahim and S. Saloum, "An efficient residue to binary converter design," IEEE Trans. Circuits Syst., vol. 35, pp. 1156-1158, Sept. 1988.
-
IEEE Trans. Circuits Syst.
-
-
Ibrahim, K.1
Saloum, S.2
-
34
-
-
0024104425
-
"A new efficient memoryless residue to binary converter,"
-
vol. 35, pp. 1441-1444, Nov. 1988.
-
S. Andraos and H. Ahmad, "A new efficient memoryless residue to binary converter," IEEE Trans. Circuits Syst., vol. 35, pp. 1441-1444, Nov. 1988.
-
IEEE Trans. Circuits Syst.
-
-
Andraos, S.1
Ahmad, H.2
-
35
-
-
0024104042
-
"Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa,"
-
vol. 35, no. 11, pp. 1425-1430, Nov. 1988.
-
R. M. Capocelli and R. Gian Carlo, "Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa," IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1425-1430, Nov. 1988.
-
IEEE Trans. Circuits Syst.
-
-
Capocelli, R.M.1
Gian Carlo, R.2
-
36
-
-
0022792027
-
"On residue number system decoding,"
-
vol. ASSP-34, no. 5, pp. 1346-1347, Oct. 1986.
-
R. Thun, "On residue number system decoding," IEEE Trans. Acoust, Speech, Signal Processing, vol. ASSP-34, no. 5, pp. 1346-1347, Oct. 1986.
-
IEEE Trans. Acoust, Speech, Signal Processing
-
-
Thun, R.1
-
37
-
-
0022769502
-
"An implementation of mixed-radix conversion for residue number applications,"
-
vol. C-35, pp. 762-764, Aug. 1986.
-
N. Chakraborti, J. Soundararajan, and A. Reddy, "An implementation of mixed-radix conversion for residue number applications," IEEE Trans. Comput., vol. C-35, pp. 762-764, Aug. 1986.
-
IEEE Trans. Comput.
-
-
Chakraborti, N.1
Soundararajan, J.2
Reddy, A.3
-
38
-
-
0022088799
-
"Efficient implementations of the Chinese reminder theorem for sign detection and residue decoding,"
-
vol. C-34, pp. 646-651, July 1985.
-
T. Van Vu, "Efficient implementations of the Chinese reminder theorem for sign detection and residue decoding," IEEE Trans. Comput., vol. C-34, pp. 646-651, July 1985.
-
IEEE Trans. Comput.
-
-
Van Vu, T.1
-
39
-
-
0022011928
-
"A new residue to decimal converter,"
-
vol. 73, pp. 378-340, Feb. 1985.
-
F. Taylor and W. Dirr Jr., "A new residue to decimal converter," Proc. IEEE, vol. 73, pp. 378-340, Feb. 1985.
-
Proc. IEEE
-
-
Taylor, F.1
Dirr Jr., W.2
-
40
-
-
0021691117
-
"A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system,"
-
vol. CAS-31, pp. 1033-1039, Dec. 1984.
-
G. Alia and E. Martinelli, "A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system," IEEE Trans. Circuits Syst., vol. CAS-31, pp. 1033-1039, Dec. 1984.
-
IEEE Trans. Circuits Syst.
-
-
Alia, G.1
Martinelli, E.2
-
41
-
-
34249093072
-
"A fast VLSI conversion between binary and residue systems,"
-
vol. 18, pp. 141-145, 1984.
-
G. Alia, F. Barsi, and E. Martinelli, "A fast VLSI conversion between binary and residue systems," IPL, vol. 18, pp. 141-145, 1984.
-
IPL
-
-
Alia, G.1
Barsi, F.2
Martinelli, E.3
-
42
-
-
0020734592
-
"A fully parallel mixed-radix conversion algorithm for residue number applications,"
-
vol. C-32, pp. 39802, Apr. 1983.
-
C. Huang, "A fully parallel mixed-radix conversion algorithm for residue number applications," IEEE Trans. Comput., vol. C-32, pp. 39802, Apr. 1983.
-
IEEE Trans. Comput.
-
-
Huang, C.1
-
43
-
-
0019654237
-
"An efficient residue-to-decimal converter,"
-
vol. CAS-28, pp. 1164-1169, Dec. 1981.
-
F. Taylor and A. S. Ramnarayanan, "An efficient residue-to-decimal converter," IEEE Trans. Circuits Syst., vol. CAS-28, pp. 1164-1169, Dec. 1981.
-
IEEE Trans. Circuits Syst.
-
-
Taylor, F.1
Ramnarayanan, A.S.2
-
44
-
-
0018038108
-
"On decoding techniques for residue number system realizations of digital signal proceesing hardware,"
-
vol. CAS-25, pp. 935-936, Nov. 1978.
-
A. Baraniecka and G. Jullien, "On decoding techniques for residue number system realizations of digital signal proceesing hardware," IEEE Trans. Circuits Syst., vol. CAS-25, pp. 935-936, Nov. 1978.
-
IEEE Trans. Circuits Syst.
-
-
Baraniecka, A.1
Jullien, G.2
-
45
-
-
0015474622
-
"On translation algorithms in residue number systems,"
-
vol. C-21,pp. 1281-1285, Dec. 1972.
-
D. Banerji and J. Brzozowski, "On translation algorithms in residue number systems,"lEEETrans. Comput., vol. C-21,pp. 1281-1285, Dec. 1972.
-
LEEETrans. Comput.
-
-
Banerji, D.1
Brzozowski, J.2
-
46
-
-
0001049670
-
"The residue number system,"
-
vol. EC-8, pp. 140-147, June 1959.
-
H. L. Garner, "The residue number system," IRE Trans. Electron. Comput., vol. EC-8, pp. 140-147, June 1959.
-
IRE Trans. Electron. Comput.
-
-
Garner, H.L.1
-
47
-
-
0032266327
-
"New Chinese remainder theorems,"
-
vol. 1, 1998, pp. 165-171.
-
Y. Wang, "New Chinese remainder theorems," in Proc. 32nd Asilomar Conf. Signals, Systems, Computers, vol. 1, 1998, pp. 165-171.
-
Proc. 32nd Asilomar Conf. Signals, Systems, Computers
-
-
Wang, Y.1
|