Diminished-one modulo 2n + 1 adder design

IEEE Transactions on Computers

Volumn 51, Issue 12, 2002, Pages 1389-1399

  Vergos, Haridimos T ^a,b   Efstathiou, Costas ^c   Nikolos, Dimitris ^a,b  

^a UNIVERSITY OF PATRAS   (Greece)

^b University of Patras and Computer Technology Institute   (Greece)

^c Informatics Department   (Greece)

Author keywords

Carry look ahead addition; Diminished one number representation; Modulo 2n + 1 addition; Parallel prefix adders; VLSI adders

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; CRYPTOGRAPHY; LOGIC DESIGN; NUMBER THEORY; PARALLEL PROCESSING SYSTEMS; RANDOM NUMBER GENERATION; RESPONSE TIME (COMPUTER SYSTEMS); VLSI CIRCUITS;

CARRY LOOK AHEAD; NUMBER SYSTEM; PARALLEL PREFIX ADDERS;

DIGITAL ARITHMETIC;

EID: 0036936883     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2002.1146705     Document Type: Article

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