Fast residue-to-binary converter architectures

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 1999, Pages 1090-1093

  Mathew, Jimson ^a   Radhakrishnan, D ^a   Srikanthan, T ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTATIONAL COMPLEXITY; DECODING; DIGITAL ARITHMETIC; FORMAL LOGIC; PARALLEL PROCESSING SYSTEMS;

CHINESE REMAINDER THEOREM; FAST RESIDUE TO BINARY CONVERTER; MIXED RADIX CONVERSION; MODULI SETS; RESIDUE NUMBER SYSTEMS;

DIGITAL SIGNAL PROCESSING;

EID: 0033292146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)