Multi-gate SOI MOSFETs

Microelectronic Engineering

Volumn 84, Issue 9-10, 2007, Pages 2071-2076

  Colinge, J P ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

Double gate FET; FinFET; GAA; MuGFET; SOI; Trigate FET

Indexed keywords

ELECTROSTATICS; QUANTUM THEORY; SILICON ON INSULATOR TECHNOLOGY;

DOUBLE-GATE FET; MUGFET; QUANTUM MODELING TOOLS; TRIGATE FET;

MOSFET DEVICES;

EID: 34249013835     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.04.038     Document Type: Article

References (42)

1. Xiong W., Ramkumar K., Jamg S.J., Park J.T., and Colinge J.P. Self-aligned ground-plane FDSOI MOSFET. Proc. IEEE International SOI Conference (2002) 23
2. T. Skotnicki, Heading for decananometer CMOS - is navigation among icebergs still a viable strategy?, Proceedings of the 30th European Solid-State Device Research Conference. (2000) 19.
3. Sekigawa T., and Hayashi Y. Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid-State Electronics 27 (1984) 827
4. Agrawal B., De V.K., Pimbley J.M., and Meindl J.D. Short channel models and scaling limits of SOI and bulk MOSFETs. IEEE Journal of Solid-State Circuits 29-2 (1994) 122
5. Hisamoto D., Kaga T., Kawamoto Y., and Takeda E. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET. Technical Digest of IEDM (1989) 833
6. Colinge J.P., Gao M.H., Romano A., Maes H., and Claeys C. Silicon-on-insulator gate-all-around device. Technical Digest of IEDM (1990) 595
7. Jurczak M., Skotnicki T., Paoli M., Tormen B., Martins J., Regolini J.L., Dutartre D., Ribot P., Lenoble D., Pantel R., and Monfray S. Silicon-on-Nothing (SON)-an innovative process for advanced CMOS. IEEE Trans. on Electron Devices 47-11 (2000) 2179
8. S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Jullian, R. Pantel, S. Descombes, et al., Highly performant double gate MOSFET realized with SON process, Technical Digest of IEDM (2003) paper 18.6.1.
9. Pretet J., Monfray S., Cristoloveanu S., and Skotnicki T. Silicon-on-nothing MOSFETs: performance, short-channel effects, and backgate coupling. IEEE Transactions on Electron Devices 51 (2002) 240
10. Liu Y., Ishii K., Tsutsumi T., Masahara M., and Suzuki E. Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching. IEEE Electron Device Letters 24-7 (2003) 484
11. T. Hiramoto, Nano-scale silicon MOSFET: towards non-traditional and quantum devices, IEEE International SOI Conference Proceedings (2001) 8.
12. Z. Jiao and A.T. Salama, A Fully Depleted Delta Channel SOI NMOSFET. Electrochem. Society Proceedings 2001-3 (2001) 403.
13. Lemme M.C., Mollenhauer T., Henschel W., Wahlbrink T., Baus M., Winkler O., Granzner R., Schwierz F., Spangenberg B., and Kurz H. Subthreshold behavior of triple-gate MOSFETs on SOI Material. Solid State Electronics 48 (2004) 529
14. X. Baie, J.P. Colinge, V. Bayot, E. Grivei, Quantum-wire effects in thin and narrow SOI MOSFETs, Proceedings IEEE International SOI Conf. (1995) 66.
15. Colinge J.P., Baie X., Bayot V., and Grivei E. A silicon-on-insulator quantum wire. Solid-State Electronics 39 (1996) 49
16. R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, S. Datta, Advanced depleted-substrate transistors: single-gate, double-gate and tri-gate, Ext. Abstr. Int. Conf. on Solid State Devices and Materials (2002) 68.
17. Doyle B.S., Datta S., Doczy M., Jin B., Kavalieros J., Linton T., Murthy A., Rios R., and Chau R. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters 24-4 (2003) 263
18. Park J.T., Colinge J.P., and Diaz C.H. Pi-gate SOI MOSFET. IEEE Electron Dev. Letters 22 (2001) 405
19. Park J.T., and Colinge J.P. Multiple-gate SOI MOSFETs: device design guidelines. IEEE Transactions on Electron Devices 49-12 (2002) 2222
20. F.L. Yang, H.Y. Chen, F.C. Cheng, C.C. Huang, C.Y. Chang, H.K. Chiu, C.C. Lee, C.C. Chen, H.T. Huang, C.J. Chen, et al., C. Hu, 25 nm CMOS Omega FETs, Technical Digest of IEDM (2002) 255.
21. Yang F.-L., Lee D.-H., Chen H.-Y., Chang C.-Y., Liu S.-D., Huang C.-C., Chung T.-X., Chen H.-W., Huang C.-C., Liu Y.-H., et al. 5nm-gate nanowire FinFET. Symp. VLSI Technology (2004) 196
22. R. Ritzenthaler, C. Dupré, X. Mescot, O. Faynot, T. Ernst, J.C. Barbé, C. Jahan, L. Brévard, F. Andrieu, S. Deleonibus, S. Cristoloveanu, Mobility behavior in narrow Ω-gate FET devices, Proceedings IEEE International SOI Conference (2006) 77.
23. Z. Krivokapic, C. Tabery, W. Maszara, Q. Xiang, M.R. Lin, High-.performance 45-nm CMOS technology with 20-nm multi-gate devices, Extended Abstracts of the International Conference on Solid State Devices and Materials (SSDM) (2003) 760.
24. 2 Gate Stack, Symposium on VLSI Technology (2006) paper 16.4.
25. J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick and R. Chau, Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering, Symposium on VLSI Technology (2006) paper 7.1.
26. Miyano S., Hirose M., and Masuoka F. Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA). IEEE Trans. Electron Dev. 39 (1992) 1876
27. Ohba T., Nakamura H., Sakuraba H., and Masuoka F. A novel tri-control gate surrounding gate transistor (TCG-SGT) nonvolatile memory cell for flash memory. Solid-State Electronics 50-6 (2005) 924
28. Nitayama, Takato H., Okabe N., Sunouchi K., Hieda K., Horiguchi F., and Masuoka F. Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits. IEEE Trans. Electron Dev. 38-3 (1991) 579
29. V. Passi, B. Olbrechts, J.P. Raskin, Fabrication of a Quadruple Gate MOSFET in Silicon-on-Insulator technology, Abstracts of the NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices (2006) 11.
30. Singh N., Agarwal A., Bera L.K., Liow T.Y., Yang R., Rustagi S.C., Tung C.H., Kumar R., Lo G.Q., Balasubramanian N., and Kwong D.L. High-performance fully depleted silicon nanowire (diameter < 5 nm) gate-all-around CMOS devices. IEEE Electron Device Letters 27-5 (2006) 383
31. Hyunjin Lee, Lee-Eun Yu, Seong-Wan Ryu, Jin-Woo Han, Kanghoon Jeon, Dong-Yoon Jang, Kuk-Hwan Kim, Jiye Lee, Ju-Hyun Kim, Sang Cheol Jeon, et al., Sub-5nm all-around gate FinFET for ultimate scaling, Symposium on VLSI Technology (2006) paper 7.5.
32. Lee S.-Y., Kim S.-M., Yoon E.-J., Oh C.W., Chung I., Park D., and Kim K. Three-dimensional MBCFET as an ultimate transistor. IEEE Electron Dev. Lett. 25-4 (2004) 217
33. Yoon E.-J., Lee S.-Y., Kim S.-M., Kim M.-S., Kim S.H., Ming L., Suk S., Yeo K., Oh C.W., Choe J.-d., et al. Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application. Technical Digest of IEDM (2005) 627
34. Donggun Park, 3 dimensional GAA transitors, twin silicon nanowire MOSFET and multi-bridge-channel MOSFET, Proc. IEEE Int. SOI Conf. (2006) 131.
35. 2/TiN Gate Stack, Technical Digest of IEDM (2006) 38.4.
36. Yan R.H., Ourmazd A., and Lee K.F. Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Transactions on Electron Devices 39-7 (1992) 1704
37. Lee C.-W., Yun S.-R.-N., Yu C.-G., Park J.-T., and Colinge J.P. Device design guidelines for nano-scale MuGFETs. Solid-State Electronics 51-3 (2007) 505
38. J.P. Colinge, Novel Gate Concepts for MOS Devices, Proceedings of ESSDERC (2004) 45.
39. Saint-Martin J., Bournel A., and Dollfus P. Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation. Solid-State Electron. 50 (2006) 94
40. Balestra F., Cristoloveanu S., Benachir M., Brini J., and Elewa T. Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance. IEEE Electron Device Letters 8-9 (1987) 410
41. Omura Y., Horiguchi S., Tabe M., and Kishi K. Quantum-mechanical effects on the threshold voltage of ultrathin SOI nMOSFETs. IEEE Electron Device Letters 14-12 (1993) 569
42. Poiroux T., Vinet M., Faynot O., Widiez J., Lolivier J., Ernst T., Previtali B., and Deleonibus S. Multiple gate devices: advantages and challenges. Microelectronic Engineering 80 (2005) 378