-
1
-
-
0036999661
-
Multiple-gate SOI MOSFETs: device design guidelines
-
Park J.T., and Colinge J.P. Multiple-gate SOI MOSFETs: device design guidelines. IEEE Trans Electron Dev 49 12 (2002) 2222-2229
-
(2002)
IEEE Trans Electron Dev
, vol.49
, Issue.12
, pp. 2222-2229
-
-
Park, J.T.1
Colinge, J.P.2
-
2
-
-
0033329310
-
Sub 50 nm FinFET: PMOS
-
Huang X., Lee W.C., Kuo C., Hisamoto D., Chang L., Kedzierski J., et al. Sub 50 nm FinFET: PMOS. Technical Digest IEDM (1999) 67-70
-
(1999)
Technical Digest IEDM
, pp. 67-70
-
-
Huang, X.1
Lee, W.C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
-
3
-
-
0038104277
-
High performance fully-depleted tri-gate CMOS transistors
-
Doyle B.S., Datta S., Doczy M., Hareland S., Jin B., Kavalieros J., et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 24 4 (2003) 263-265
-
(2003)
IEEE Electron Dev Lett
, vol.24
, Issue.4
, pp. 263-265
-
-
Doyle, B.S.1
Datta, S.2
Doczy, M.3
Hareland, S.4
Jin, B.5
Kavalieros, J.6
-
5
-
-
0036932378
-
25 nm CMOS omega FETs
-
Yang F.L., et al. 25 nm CMOS omega FETs. Technical Digest IEDM (2002) 255-258
-
(2002)
Technical Digest IEDM
, pp. 255-258
-
-
Yang, F.L.1
-
6
-
-
0025575976
-
Silicon-on-insulator gate-all-around device
-
Colinge J.P., Gao M.H., Rodriguez A.R., Maes H., and Claeys C. Silicon-on-insulator gate-all-around device. Technical Digest IEDM (1990) 595-598
-
(1990)
Technical Digest IEDM
, pp. 595-598
-
-
Colinge, J.P.1
Gao, M.H.2
Rodriguez, A.R.3
Maes, H.4
Claeys, C.5
-
7
-
-
1442360362
-
Multiple-gate SOI MOSFETs
-
Colinge J.P. Multiple-gate SOI MOSFETs. Solid-State Electron 48 6 (2004) 897-905
-
(2004)
Solid-State Electron
, vol.48
, Issue.6
, pp. 897-905
-
-
Colinge, J.P.1
-
8
-
-
85054396782
-
-
Ernst T, Muteanu D, Cristoloveanu S, Ouisse T, Hefyene N, Horiguchi S, et al. Ultimately thin SOI MOSFETs: special characteristics and mechanisms. In: Proceedings of the IEEE international SOI conference, 1999. p. 92-3.
-
-
-
-
9
-
-
0142154785
-
-
Xiong W, Park JW, Colinge JP. Corner effect in multiple-gate SOI MOSFETs. In: Proceedings of the IEEE international SOI conference, 2003. p. 111-3.
-
-
-
-
10
-
-
0042888776
-
Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs
-
Colinge J.P., Park J.W., and Xing W. Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs. IEEE Electron Dev Lett 24 8 (2003) 515-517
-
(2003)
IEEE Electron Dev Lett
, vol.24
, Issue.8
, pp. 515-517
-
-
Colinge, J.P.1
Park, J.W.2
Xing, W.3
-
11
-
-
0347131289
-
Suppression of corner effects in triple-gate MOSFETs
-
Fossum J.G., Yang J.W., and Trivedi V.P. Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Dev Lett 24 12 (2003) 745-747
-
(2003)
IEEE Electron Dev Lett
, vol.24
, Issue.12
, pp. 745-747
-
-
Fossum, J.G.1
Yang, J.W.2
Trivedi, V.P.3
-
12
-
-
20244383595
-
-
Städele M, Luyken RJ, Roosz M, Specht M, Rosner W, Dreeskornfeld L, et al. A comprehensive study of corner effects in tri-gate transistors. In: Proceedings 34th ESSDERC, 2004. p. 165-8.
-
-
-
-
13
-
-
3943054085
-
Improvement of FinFET electrical characteristics by hydrogen annealing
-
Xiong W., Gebara G., Zaman J., Gostkowski M., Nguyen B., Smith G., et al. Improvement of FinFET electrical characteristics by hydrogen annealing. IEEE Electron Dev Lett 25 8 (2004) 74-76
-
(2004)
IEEE Electron Dev Lett
, vol.25
, Issue.8
, pp. 74-76
-
-
Xiong, W.1
Gebara, G.2
Zaman, J.3
Gostkowski, M.4
Nguyen, B.5
Smith, G.6
-
14
-
-
0141761518
-
-
Doyle BS, Boyanov B, Doczy M, Hareland S, Jin B, Kavalieros J, et al. Tri-gate fully-depleted CMOS transistors: fabrication, design and layout. In: Proceeding of symposium of VLSI technology, 2003. p. 133-4.
-
-
-
-
15
-
-
33947670516
-
-
http://www.silvaco.com.
-
-
-
-
16
-
-
0026896303
-
Scaling the Si MOSFET: from Bulk to SOI to Bulk
-
Yan R.H., Ourmazd A., and Lee K.F. Scaling the Si MOSFET: from Bulk to SOI to Bulk. IEEE Trans Electron Dev 39 7 (1992) 1704-1710
-
(1992)
IEEE Trans Electron Dev
, vol.39
, Issue.7
, pp. 1704-1710
-
-
Yan, R.H.1
Ourmazd, A.2
Lee, K.F.3
-
17
-
-
0027847411
-
Scaling theory for double-gate SOI MOSFET's
-
Suzuki K., Tanaka T., Tosaka Y., Horie H., and Arimoto Y. Scaling theory for double-gate SOI MOSFET's. IEEE Trans Electron Dev 40 12 (1993) 2326-2329
-
(1993)
IEEE Trans Electron Dev
, vol.40
, Issue.12
, pp. 2326-2329
-
-
Suzuki, K.1
Tanaka, T.2
Tosaka, Y.3
Horie, H.4
Arimoto, Y.5
-
18
-
-
0032205525
-
A simple model for threshold voltage of surrounding-gate MOSFET's
-
Auth C.P., and Plummer J.D. A simple model for threshold voltage of surrounding-gate MOSFET's. IEEE Trans Electron Dev 45 11 (1998) 2381-2383
-
(1998)
IEEE Trans Electron Dev
, vol.45
, Issue.11
, pp. 2381-2383
-
-
Auth, C.P.1
Plummer, J.D.2
-
19
-
-
0032070926
-
Semiconductor thickness effects in the double-gate SOI MOSFET
-
Majkusiak B., Janik T., and Walczak J. Semiconductor thickness effects in the double-gate SOI MOSFET. IEEE Trans Electron Dev 45 5 (1998) 1127-1134
-
(1998)
IEEE Trans Electron Dev
, vol.45
, Issue.5
, pp. 1127-1134
-
-
Majkusiak, B.1
Janik, T.2
Walczak, J.3
-
20
-
-
0031079417
-
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
-
Auth C.P., and Plummer J.D. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's. IEEE Electron Dev Lett 18 2 (1997) 74-76
-
(1997)
IEEE Electron Dev Lett
, vol.18
, Issue.2
, pp. 74-76
-
-
Auth, C.P.1
Plummer, J.D.2
-
21
-
-
21044449128
-
Analysis of the parasitic S/D resistance in multiple-gate FETs
-
Dixit A., Kottantharayil A., Collaert N., Goodwin M., Jurczak M., and DeMeyer K. Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans Electron Dev 52 6 (2005) 1132-1140
-
(2005)
IEEE Trans Electron Dev
, vol.52
, Issue.6
, pp. 1132-1140
-
-
Dixit, A.1
Kottantharayil, A.2
Collaert, N.3
Goodwin, M.4
Jurczak, M.5
DeMeyer, K.6
-
22
-
-
0023422261
-
Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs
-
Wong H.S., White M.H., Krutsck T.J., and Booth R.V. Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs. Solid-State Electron 30 9 (1987) 953-968
-
(1987)
Solid-State Electron
, vol.30
, Issue.9
, pp. 953-968
-
-
Wong, H.S.1
White, M.H.2
Krutsck, T.J.3
Booth, R.V.4
-
23
-
-
0028427763
-
Modeling of ultrathin double-gate SOI
-
Francis P., terao A., Flandre D., and Van de Wiele F. Modeling of ultrathin double-gate SOI. Solid-State Electron 41 5 (1994) 715-720
-
(1994)
Solid-State Electron
, vol.41
, Issue.5
, pp. 715-720
-
-
Francis, P.1
terao, A.2
Flandre, D.3
Van de Wiele, F.4
|