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Volumn 51, Issue 3, 2007, Pages 505-510

Device design guidelines for nano-scale MuGFETs

Author keywords

Field effect transistors; MOSFET; Multi gate MOSFET; Silicon on insulator

Indexed keywords

GATE DIELECTRICS; PERMITTIVITY; SILICON; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

EID: 33947678825     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.11.013     Document Type: Article
Times cited : (106)

References (23)
  • 1
    • 0036999661 scopus 로고    scopus 로고
    • Multiple-gate SOI MOSFETs: device design guidelines
    • Park J.T., and Colinge J.P. Multiple-gate SOI MOSFETs: device design guidelines. IEEE Trans Electron Dev 49 12 (2002) 2222-2229
    • (2002) IEEE Trans Electron Dev , vol.49 , Issue.12 , pp. 2222-2229
    • Park, J.T.1    Colinge, J.P.2
  • 5
    • 0036932378 scopus 로고    scopus 로고
    • 25 nm CMOS omega FETs
    • Yang F.L., et al. 25 nm CMOS omega FETs. Technical Digest IEDM (2002) 255-258
    • (2002) Technical Digest IEDM , pp. 255-258
    • Yang, F.L.1
  • 7
    • 1442360362 scopus 로고    scopus 로고
    • Multiple-gate SOI MOSFETs
    • Colinge J.P. Multiple-gate SOI MOSFETs. Solid-State Electron 48 6 (2004) 897-905
    • (2004) Solid-State Electron , vol.48 , Issue.6 , pp. 897-905
    • Colinge, J.P.1
  • 8
    • 85054396782 scopus 로고    scopus 로고
    • Ernst T, Muteanu D, Cristoloveanu S, Ouisse T, Hefyene N, Horiguchi S, et al. Ultimately thin SOI MOSFETs: special characteristics and mechanisms. In: Proceedings of the IEEE international SOI conference, 1999. p. 92-3.
  • 9
    • 0142154785 scopus 로고    scopus 로고
    • Xiong W, Park JW, Colinge JP. Corner effect in multiple-gate SOI MOSFETs. In: Proceedings of the IEEE international SOI conference, 2003. p. 111-3.
  • 10
    • 0042888776 scopus 로고    scopus 로고
    • Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs
    • Colinge J.P., Park J.W., and Xing W. Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs. IEEE Electron Dev Lett 24 8 (2003) 515-517
    • (2003) IEEE Electron Dev Lett , vol.24 , Issue.8 , pp. 515-517
    • Colinge, J.P.1    Park, J.W.2    Xing, W.3
  • 11
    • 0347131289 scopus 로고    scopus 로고
    • Suppression of corner effects in triple-gate MOSFETs
    • Fossum J.G., Yang J.W., and Trivedi V.P. Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Dev Lett 24 12 (2003) 745-747
    • (2003) IEEE Electron Dev Lett , vol.24 , Issue.12 , pp. 745-747
    • Fossum, J.G.1    Yang, J.W.2    Trivedi, V.P.3
  • 12
    • 20244383595 scopus 로고    scopus 로고
    • Städele M, Luyken RJ, Roosz M, Specht M, Rosner W, Dreeskornfeld L, et al. A comprehensive study of corner effects in tri-gate transistors. In: Proceedings 34th ESSDERC, 2004. p. 165-8.
  • 14
    • 0141761518 scopus 로고    scopus 로고
    • Doyle BS, Boyanov B, Doczy M, Hareland S, Jin B, Kavalieros J, et al. Tri-gate fully-depleted CMOS transistors: fabrication, design and layout. In: Proceeding of symposium of VLSI technology, 2003. p. 133-4.
  • 15
    • 33947670516 scopus 로고    scopus 로고
    • http://www.silvaco.com.
  • 16
    • 0026896303 scopus 로고
    • Scaling the Si MOSFET: from Bulk to SOI to Bulk
    • Yan R.H., Ourmazd A., and Lee K.F. Scaling the Si MOSFET: from Bulk to SOI to Bulk. IEEE Trans Electron Dev 39 7 (1992) 1704-1710
    • (1992) IEEE Trans Electron Dev , vol.39 , Issue.7 , pp. 1704-1710
    • Yan, R.H.1    Ourmazd, A.2    Lee, K.F.3
  • 18
    • 0032205525 scopus 로고    scopus 로고
    • A simple model for threshold voltage of surrounding-gate MOSFET's
    • Auth C.P., and Plummer J.D. A simple model for threshold voltage of surrounding-gate MOSFET's. IEEE Trans Electron Dev 45 11 (1998) 2381-2383
    • (1998) IEEE Trans Electron Dev , vol.45 , Issue.11 , pp. 2381-2383
    • Auth, C.P.1    Plummer, J.D.2
  • 19
    • 0032070926 scopus 로고    scopus 로고
    • Semiconductor thickness effects in the double-gate SOI MOSFET
    • Majkusiak B., Janik T., and Walczak J. Semiconductor thickness effects in the double-gate SOI MOSFET. IEEE Trans Electron Dev 45 5 (1998) 1127-1134
    • (1998) IEEE Trans Electron Dev , vol.45 , Issue.5 , pp. 1127-1134
    • Majkusiak, B.1    Janik, T.2    Walczak, J.3
  • 20
    • 0031079417 scopus 로고    scopus 로고
    • Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
    • Auth C.P., and Plummer J.D. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's. IEEE Electron Dev Lett 18 2 (1997) 74-76
    • (1997) IEEE Electron Dev Lett , vol.18 , Issue.2 , pp. 74-76
    • Auth, C.P.1    Plummer, J.D.2
  • 22
    • 0023422261 scopus 로고
    • Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs
    • Wong H.S., White M.H., Krutsck T.J., and Booth R.V. Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs. Solid-State Electron 30 9 (1987) 953-968
    • (1987) Solid-State Electron , vol.30 , Issue.9 , pp. 953-968
    • Wong, H.S.1    White, M.H.2    Krutsck, T.J.3    Booth, R.V.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.