Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Ernst, T ^a   Dupre C ^a,b   Isheden, C ^a   Bernard, E ^a,c   Ritzenthaler, R ^a   Maffini Alvaro, V ^a   Barbe J C ^a   De Crecy, F ^a   Toffoli, A ^a   Vizioz, C ^a   Borel, S ^a   Andrieu, F ^a   Delaye, V ^a   Lafond, D ^a   Rabille G ^a,c   Hartmann, J M ^a   Rivoire, M ^a,c   Guillaumot, B ^a,c   Suhm, A ^a   Rivallin, P ^a   Faynot, O ^a   Ghibaudo, G ^a,b   Deleonibus, S ^a   more..

^a CEA LETI   (France)

^b IMEP LAHC   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; ELECTRON DEVICES; HAFNIUM COMPOUNDS; LOGIC GATES; SILICON;

3-D INTEGRATION; CMOS GATES; FINFETS; GA TE LENGTHS; GATE STACKS; PLANAR TRANSISTORS;

GALLIUM ALLOYS;

EID: 46049086980     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346955     Document Type: Conference Paper

References (11)

1. B. Doyle et al., VLSI Tech Symp, p. 133, 2003
2. F.-L. Yang et al., VLSI Tech Symp, p. 196, 2004
3. S. D. Suk et al., IEDM 2005, p. 717.
4. S.-Y. Lee. et al., VLSI Tech Symp, p.200, 2004
5. M.-S. Kim et al., VLSI T. Symp, p.84, 2006
6. S. Monfray et al., VLSI Techn symp, p.108, 2002
7. S. Borel et al., Micro. Eng., vol 73C pp 301, 2004
8. B. Guillaumot et al., IEDM 2002, p. 355.
9. G. Ghibaudo, Elec. Let. Vol. 24, p. 543, 1988
10. M. F. Hamer, IEE proc., vol. 133 I, 1986
11. K. Romanjek, IEEE Elec. Dev. Let., vol 25, p.583, 2004