-
2
-
-
0036917242
-
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
-
S. Martin, K. Flautner, T. Mudge, and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in Proc. Int. Conf. Comput.-Aided Des., 2002, pp. 721-725.
-
(2002)
Proc. Int. Conf. Comput.-Aided Des
, pp. 721-725
-
-
Martin, S.1
Flautner, K.2
Mudge, T.3
Blaauw, D.4
-
3
-
-
0029488569
-
A scheduling model for reduced CPU energy
-
F. Yao, A. Demers, and S. Shenker, "A scheduling model for reduced CPU energy," in Proc. IEEE Symp. Foundations Comput. Sci, 1995, pp. 374-382.
-
(1995)
Proc. IEEE Symp. Foundations Comput. Sci
, pp. 374-382
-
-
Yao, F.1
Demers, A.2
Shenker, S.3
-
4
-
-
84893738755
-
Dynamic Vth scaling scheme for active leakage power reduction
-
C. Kim and K. Roy, "Dynamic Vth scaling scheme for active leakage power reduction," in Proc. Design, Autom. Test Eur. Conf., 2002, pp. 163-167.
-
(2002)
Proc. Design, Autom. Test Eur. Conf
, pp. 163-167
-
-
Kim, C.1
Roy, K.2
-
5
-
-
0032592096
-
Design challenges of technology scaling
-
Jul
-
S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23-29, Jul. 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.4
, pp. 23-29
-
-
Borkar, S.1
-
6
-
-
33645222076
-
Optimal voltage allocation techniques for dynamically variable voltage processors
-
Feb
-
W. Kwon and T. Kim, "Optimal voltage allocation techniques for dynamically variable voltage processors," ACM Trans. Embed. Comput. Syst., vol. 4, pp. 211-230, Feb. 2005.
-
(2005)
ACM Trans. Embed. Comput. Syst
, vol.4
, pp. 211-230
-
-
Kwon, W.1
Kim, T.2
-
7
-
-
84949801414
-
LEneS: Task scheduling for low-energy systems using variable supply voltage processors
-
F. Gruian and K. Kuchcinski, "LEneS: Task scheduling for low-energy systems using variable supply voltage processors," in Proc. ASP-DAC, 2001, pp. 449-455.
-
(2001)
Proc. ASP-DAC
, pp. 449-455
-
-
Gruian, F.1
Kuchcinski, K.2
-
8
-
-
84941360711
-
Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems
-
J. Luo and N. Jha, "Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems," in Proc. VLSI, 2003, pp. 369-375.
-
(2003)
Proc. VLSI
, pp. 369-375
-
-
Luo, J.1
Jha, N.2
-
9
-
-
0034785240
-
Considering power variations of DVS processing elements for energy minimization in distributed systems
-
M. Schmitz and B. M. Al-Hashimi, "Considering power variations of DVS processing elements for energy minimization in distributed systems," in Proc. Int. Symp. Syst. Synthesis, 2001, pp. 250-255.
-
(2001)
Proc. Int. Symp. Syst. Synthesis
, pp. 250-255
-
-
Schmitz, M.1
Al-Hashimi, B.M.2
-
10
-
-
0036056702
-
Task scheduling and voltage selection for energy minimization
-
Y. Zhang, X. Hu, and D. Chen, "Task scheduling and voltage selection for energy minimization," in Proc. Des. Autom. Conf., 2002, pp. 183-188.
-
(2002)
Proc. Des. Autom. Conf
, pp. 183-188
-
-
Zhang, Y.1
Hu, X.2
Chen, D.3
-
11
-
-
0036396948
-
Impact of scaling on the effectiveness of dynamic power reduction
-
D. Duarte, N. Vijaykrishnan, M. Irwin, H. Kim, and G. McFarland, "Impact of scaling on the effectiveness of dynamic power reduction," in Proc. ICCD, 2002, pp. 382-387.
-
(2002)
Proc. ICCD
, pp. 382-387
-
-
Duarte, D.1
Vijaykrishnan, N.2
Irwin, M.3
Kim, H.4
McFarland, G.5
-
12
-
-
0032301840
-
Synthesis techniques for low-power hard real-time systems on variable voltage processors
-
I. Hong, G. Qu, M. Potkonjak, and M. B. Srivastava, "Synthesis techniques for low-power hard real-time systems on variable voltage processors," in Proc. Real-Time Syst. Symp., 1998, pp. 178-187.
-
(1998)
Proc. Real-Time Syst. Symp
, pp. 178-187
-
-
Hong, I.1
Qu, G.2
Potkonjak, M.3
Srivastava, M.B.4
-
13
-
-
0036911949
-
A realistic variable voltage scheduling model for real-time applications
-
B. Mochocki, X. Hu, and G. Quan, "A realistic variable voltage scheduling model for real-time applications," in Proc. Int. Conf. Comput.-Aided Des., 2002, pp. 726-731.
-
(2002)
Proc. Int. Conf. Comput.-Aided Des
, pp. 726-731
-
-
Mochocki, B.1
Hu, X.2
Quan, G.3
-
14
-
-
3042546147
-
Energy minimization of real-time tasks on variable voltage processors with transition energy overhead
-
Y. Zhang, X. Hu, and D. Chen, "Energy minimization of real-time tasks on variable voltage processors with transition energy overhead," in Proc. ASP-DAC, 2003, pp. 65-70.
-
(2003)
Proc. ASP-DAC
, pp. 65-70
-
-
Zhang, Y.1
Hu, X.2
Chen, D.3
-
15
-
-
22544455956
-
Joint dynamic voltage scaling and adpative body biasing for heterogeneous distributed real-time embedded systems
-
Jul
-
L. Yan, J. Luo, and N. Jha, "Joint dynamic voltage scaling and adpative body biasing for heterogeneous distributed real-time embedded systems," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 7, pp. 1030-1041, Jul. 2005.
-
(2005)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst
, vol.24
, Issue.7
, pp. 1030-1041
-
-
Yan, L.1
Luo, J.2
Jha, N.3
-
16
-
-
27944494362
-
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems
-
R. G. R. Jejurikar, "Dynamic slack reclamation with procrastination scheduling in real-time embedded systems," in Proc. Des. Autom. Conf., 2005, pp. 111-116.
-
(2005)
Proc. Des. Autom. Conf
, pp. 111-116
-
-
Jejurikar, R.G.R.1
-
17
-
-
0035392122
-
Optimum voltage swing on on-chip and off-chip interconnects
-
Jul
-
C. Svensson, "Optimum voltage swing on on-chip and off-chip interconnects," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1108-1112, Jul. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.7
, pp. 1108-1112
-
-
Svensson, C.1
-
18
-
-
33646924323
-
Impact of small process geometries on microarchitectures in systems on a chip
-
Apr
-
D. Sylvester and K. Keutzer, "Impact of small process geometries on microarchitectures in systems on a chip," Proc. IEEE, vol. 89, no. 4, pp. 467-489, Apr. 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.4
, pp. 467-489
-
-
Sylvester, D.1
Keutzer, K.2
-
19
-
-
0032633647
-
Repeater insertion in RLC lines for minimum propagation delay
-
Y. Ismail and E. Friedman, "Repeater insertion in RLC lines for minimum propagation delay," in Proc. ISCAS, 1999, pp. 404-407.
-
(1999)
Proc. ISCAS
, pp. 404-407
-
-
Ismail, Y.1
Friedman, E.2
-
20
-
-
0036046921
-
Power estimation in global interconnects and its reduction using a novel repeater optimization methodology
-
P. Kapur, G. Chandra, and K. Saraswat, "Power estimation in global interconnects and its reduction using a novel repeater optimization methodology," in Proc. DAC, 2002, pp. 461-466.
-
(2002)
Proc. DAC
, pp. 461-466
-
-
Kapur, P.1
Chandra, G.2
Saraswat, K.3
-
21
-
-
85008055290
-
Power-efficient interconnection networks: Dynamic voltage scaling with links
-
May
-
L. Shang, L. Peh, and N. Jha, "Power-efficient interconnection networks: Dynamic voltage scaling with links," Comp. Arch. Lett., vol. 1, no. 2, pp. 1-4, May 2002.
-
(2002)
Comp. Arch. Lett
, vol.1
, Issue.2
, pp. 1-4
-
-
Shang, L.1
Peh, L.2
Jha, N.3
-
22
-
-
0034314916
-
A variable-frequency parallel I/O interface with adaptive power-supply regulation
-
Nov
-
G. Wei, J. Kim, D. Liu, S. Sidiropoulos, and M. Horowitz, "A variable-frequency parallel I/O interface with adaptive power-supply regulation," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1600-1610, Nov. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1600-1610
-
-
Wei, G.1
Kim, J.2
Liu, D.3
Sidiropoulos, S.4
Horowitz, M.5
-
23
-
-
0036047181
-
Communication speed selection for embedded systems with networked voltage-scalable processors
-
J. Liu, P. Chou, and N. Bagherzdeh, "Communication speed selection for embedded systems with networked voltage-scalable processors," in Proc. CODES, 2002, pp. 169-174.
-
(2002)
Proc. CODES
, pp. 169-174
-
-
Liu, J.1
Chou, P.2
Bagherzdeh, N.3
-
24
-
-
84893775814
-
Address bus encoding techniques for system-level power optimization
-
L. Benini, G. D. Micheli, E. Macii, D. Sciuto, and C. Silvano, "Address bus encoding techniques for system-level power optimization," in Proc. DATE, 1998, pp. 861-867.
-
(1998)
Proc. DATE
, pp. 861-867
-
-
Benini, L.1
Micheli, G.D.2
Macii, E.3
Sciuto, D.4
Silvano, C.5
-
25
-
-
0036540701
-
Architectural energy optimization by bus splitting
-
Apr
-
C.-T. Hsieh and M. Pedram, "Architectural energy optimization by bus splitting," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 4, pp. 408-414, Apr. 2002.
-
(2002)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst
, vol.21
, Issue.4
, pp. 408-414
-
-
Hsieh, C.-T.1
Pedram, M.2
-
26
-
-
0032683154
-
Power estimation for architectural exploration of HW/SW communication on system-level buses
-
W. Fornaciari, D. Sciuto, and C. Silvano, "Power estimation for architectural exploration of HW/SW communication on system-level buses," in Proc. 7th Int. Workshop Hardw./Softw. Co-Design(CODES), 1999, pp. 152-156.
-
(1999)
Proc. 7th Int. Workshop Hardw./Softw. Co-Design(CODES)
, pp. 152-156
-
-
Fornaciari, W.1
Sciuto, D.2
Silvano, C.3
-
27
-
-
0346148453
-
Communication-aware task scheduling and voltage selection for total system energy minimization
-
G. Varatkar and R. Marculescu, "Communication-aware task scheduling and voltage selection for total system energy minimization," in Proc. Int. Conf. Comput.-Aided Des., 2003, pp. 510-517.
-
(2003)
Proc. Int. Conf. Comput.-Aided Des
, pp. 510-517
-
-
Varatkar, G.1
Marculescu, R.2
-
28
-
-
3042565410
-
Overhead-conscious voltage selection for dynamic and leakage power reduction of time-constraint systems
-
A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. Al-Hashimi, "Overhead-conscious voltage selection for dynamic and leakage power reduction of time-constraint systems," in Proc. Des., Autom. Test Eur. Conf., 2004, pp. 518-523.
-
(2004)
Proc. Des., Autom. Test Eur. Conf
, pp. 518-523
-
-
Andrei, A.1
Schmitz, M.2
Eles, P.3
Peng, Z.4
Al-Hashimi, B.5
-
29
-
-
16244423681
-
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems
-
_, "Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems," in Proc. Int. Conf. Comput.-Aided Des., 2004, pp. 362-369.
-
(2004)
Proc. Int. Conf. Comput.-Aided Des
, pp. 362-369
-
-
Andrei, A.1
Schmitz, M.2
Eles, P.3
Peng, Z.4
Al-Hashimi, B.5
-
30
-
-
34247096854
-
-
Dept. Comput. Inf. Sci, Linköping Univ, Linköping, Sweden, Tech. Rep
-
_, "Energy optimization of multiprocessor systems on chip by voltage selection," Dept. Comput. Inf. Sci., Linköping Univ., Linköping, Sweden, 2007, Tech. Rep..
-
(2007)
Energy optimization of multiprocessor systems on chip by voltage selection
-
-
Andrei, A.1
Schmitz, M.2
Eles, P.3
Peng, Z.4
Al-Hashimi, B.5
-
31
-
-
29144484027
-
Quasi-static voltage scaling for energy minimization with time constraints
-
_, "Quasi-static voltage scaling for energy minimization with time constraints," in Proc. DATE, 2005, pp. 514-519.
-
(2005)
Proc. DATE
, pp. 514-519
-
-
Andrei, A.1
Schmitz, M.2
Eles, P.3
Peng, Z.4
Al-Hashimi, B.5
-
33
-
-
34247105216
-
-
Intel, Santa Clara, CA, Intel XScale Core, Developer's Manual, 2000.
-
Intel, Santa Clara, CA, "Intel XScale Core, Developer's Manual," 2000.
-
-
-
-
34
-
-
34247149231
-
Mobile AMD Athlon 4, Processor Model 6 CPGA Data Sheet
-
Tech. Rep. 24319 Rev E
-
AMD, Sunnyvale, CA, "Mobile AMD Athlon 4, Processor Model 6 CPGA Data Sheet," Tech. Rep. 24319 Rev E, 2000.
-
(2000)
-
-
AMD, S.C.A.1
-
35
-
-
0003254248
-
Interior-point polynomial algorithms in convex programming
-
Philadelphia, PA: SIAM
-
Y. Nesterov and A. Nemirovskii, "Interior-point polynomial algorithms in convex programming," in Studies in Applied Mathematics. Philadelphia, PA: SIAM, 1994.
-
(1994)
Studies in Applied Mathematics
-
-
Nesterov, Y.1
Nemirovskii, A.2
-
36
-
-
16244418878
-
Low-power, low-latency global interconnects
-
P. Caputa and C. Svensson, "Low-power, low-latency global interconnects," in Proc. IEEE ASIC/SOC, 2002, pp. 394-398.
-
(2002)
Proc. IEEE ASIC/SOC
, pp. 394-398
-
-
Caputa, P.1
Svensson, C.2
-
38
-
-
84954421164
-
Energy-aware mapping for tile-based NoC architectures under performance constraints
-
J. Hu and R. Marculescu, "Energy-aware mapping for tile-based NoC architectures under performance constraints," in Proc. ASPDAC, 2003. pp. 233-239.
-
(2003)
Proc. ASPDAC
, pp. 233-239
-
-
Hu, J.1
Marculescu, R.2
-
39
-
-
34247100981
-
A cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MP-SoCs
-
M. Ruggiero, P. Gioia, G. Alessio, L. B. M. Milano, D. Bertozzi, and A. Andrei, "A cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MP-SoCs," in Proc. Int. Symp. Syst.-on-Chip, 2007, pp. 1-4.
-
(2007)
Proc. Int. Symp. Syst.-on-Chip
, pp. 1-4
-
-
Ruggiero, M.1
Gioia, P.2
Alessio, G.3
Milano, L.B.M.4
Bertozzi, D.5
Andrei, A.6
-
40
-
-
13144261760
-
Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities
-
Feb
-
M. Schmitz, B. Al-Hashimi, and P. Eles, "Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 2, pp. 153-169, Feb. 2005.
-
(2005)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst
, vol.24
, Issue.2
, pp. 153-169
-
-
Schmitz, M.1
Al-Hashimi, B.2
Eles, P.3
|