-
1
-
-
84950155377
-
The Alpha 21364 network architecture
-
Aug.
-
S. Mukherjee, P. Bannon, S. Lang A. Spink, and D. Webb, “The Alpha 21364 network architecture,” in Proc. Hot Interconnects 9, Aug. 2001.
-
(2001)
Proc. Hot Interconnects 9
-
-
Mukherjee, S.1
Bannon, P.2
Lang, S.3
Spink, A.4
Webb, D.5
-
2
-
-
0029254155
-
Myrinet - a Gigabit-per-second local-area-network
-
Feb.
-
N. Boden et al., “Myrinet - a Gigabit-per-second local-area-network,” IEEE Micro, vol. 15, no. 1, pp. 29–36, Feb. 1995.
-
(1995)
IEEE Micro
, vol.15
, Issue.1
, pp. 29-36
-
-
Boden, N.1
-
3
-
-
85008061891
-
The Inifiniband architecture
-
http://www. infinibandta.orq.
-
The Inifiniband architecture, http://www.infinibandta.orq.
-
-
-
-
4
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
June
-
W. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks,” in Proc. Design Automation Conf., pp. 684–689, June 2001.
-
(2001)
Proc. Design Automation Conf., pp.
, pp. 684-689
-
-
Dally, W.1
Towles, B.2
-
5
-
-
0035063030
-
A 1.2 GHz Alpha microprocessor with 44.8GB/s chip pin bandwidth
-
Feb.
-
A. Jain et al., “A 1.2 GHz Alpha microprocessor with 44.8GB/s chip pin bandwidth,” in Proc. Int. Sold-State Circuits Conf., pp. 240–241, Feb. 2001.
-
(2001)
Proc. Int. Sold-State Circuits Conf., pp.
, pp. 240-241
-
-
Jain, A.1
-
7
-
-
85008003165
-
microarchitecture
-
http://developer. intel.com/de-sign/intelxscalet
-
Intel XScale microarchitecture, http://developer.intel.com/de-sign/intelxscalet
-
-
-
Intel, X.1
-
9
-
-
0034314916
-
A variable-frequency parallel I/O interface with adaptive power-supply regulation
-
Nov.
-
G. Wei, J. Kim, D. Liu, S. Sidiropoulos, and M. Horowitz, “A variable-frequency parallel I/O interface with adaptive power-supply regulation,” J. Solid-State Circuits, vol. 35, no. 11, pp. 1600–1610, Nov. 2000.
-
(2000)
J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1600-1610
-
-
Wei, G.1
Kim, J.2
Liu, D.3
Sidiropoulos, S.4
Horowitz, M.5
-
10
-
-
1542326696
-
Adaptive supply serial links with sub-IV operation and per-pin clock recovery
-
Feb.
-
J. Kim and M. Horowitz, “Adaptive supply serial links with sub-IV operation and per-pin clock recovery,” in Proc. Int. Solid-State Circuits Conf., Feb. 2002.
-
(2002)
Proc. Int. Solid-State Circuits Conf.
-
-
Kim, J.1
Horowitz, M.2
-
11
-
-
0031373275
-
Power-constrained design of multiprocessor interconnection networks
-
Oct.
-
C. Patel, S. Chai, S. Yalamanchili, and D. Schimmel, “Power-constrained design of multiprocessor interconnection networks,” in Proc. Int. Conf. Computer Design, pp. 408–416, Oct. 1997.
-
(1997)
Proc. Int. Conf. Computer Design, pp.
, pp. 408-416
-
-
Patel, C.1
Chai, S.2
Yalamanchili, S.3
Schimmel, D.4
-
12
-
-
85008008992
-
Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs
-
Apr.
-
H. Zhang, M. Wan, V. George and J. Rabaey, “Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs,” in Proc. Workshop VLSI, pp. 2–8, Apr. 1999.
-
(1999)
Proc. Workshop VLSI, pp.
, pp. 2-8
-
-
Zhang, H.1
Wan, M.2
George, V.3
Rabaey, J.4
-
13
-
-
0004051569
-
High-effciency low-voltage DC-DC conversionfor portable applications
-
Ph.D. Thesis, Univ. of California, Berkeley June
-
A. Stratakos, “High-effciency low-voltage DC-DC conversionfor portable applications,” Ph.D. Thesis, Univ. of California, Berkeley June 1998.
-
(1998)
-
-
Stratakos, A.1
-
14
-
-
0026825968
-
Virtual-channel flow control
-
Mar.
-
W. Dally, “Virtual-channel flow control,” IEEE Trans. Parallel Distributed Systems, vol. 3, no. 2 pp. 194–205, Mar. 1992.
-
(1992)
IEEE Trans. Parallel Distributed Systems
, vol.3
, Issue.2
, pp. 194-205
-
-
Dally, W.1
-
15
-
-
0034818435
-
A delay model and speculative architecture for pipelined routers
-
Jan.
-
L. Peh and W. Dally, “A delay model and speculative architecture for pipelined routers,” in Proc. High-Performance Computer Architecture, pp. 255–266, Jan. 2001.
-
(2001)
Proc. High-Performance Computer Architecture
, pp. 255-266
-
-
Peh, L.1
Dally, W.2
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