Communication speed selection for embedded systems with networked voltage-scalable processors

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2002, Pages 169-174

  Liu, Jinfeng ^a   Chou, Pai H ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; DATA COMMUNICATION SYSTEMS; ENERGY UTILIZATION; IMAGE PROCESSING; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS); VOLTAGE CONTROL;

COMMUNICATION SPEED SELECTION; DYNAMIC VOLTAGE SCALING; MULTIPROCESSOR ARCHITECTURE;

EMBEDDED SYSTEMS;

EID: 0036047181     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774821.774824     Document Type: Conference Paper

References (11)

1. INTEL ethernet PHYs/transceiver
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6. Integrating communication protocol selection with hardware/software codesign
7. Battery-aware static scheduling for distributed real-time embedded systems
8. Communication synthesis for distributed embedded systems
9. Signal to clutter measurement and ATR performance
10. Minimizing energy consumption for high-performance processing
11. An architectural co-synthesis algorithm for distributed embedded computing systems