Low-power, low-latency global interconnect

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 394-398

  Caputa, Peter ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

GLOBAL INTERCONNECTS; LOW LATENCY; LOW POWER; SIMPLE SCHEMES; VOLTAGE SWINGS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 16244418878     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158091     Document Type: Conference Paper

References (6)

1. W.J. Dally and J.W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.
2. C. Svensson, Electrical Interconnects Revitalized, manuscript, www.ek.isy,liu,se/~christeit/MamiscriptSwing,pdf.
3. C. Svensson, Optimum Voltage Swing on On-Chip and Off-Chip Interconnect, IEEE Journal of Solid-State Circuits, Vol. 36, No. 7, pp. 1108-1112, July 2001.
4. TSMC 0.18 μm Logic Salicide process.
5. Advanced Mixed-Signal and RFCMOS Solutions, Chartered Semiconductors, 2001.
6. Corrected formulas from [1]