Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability

Solid-State Electronics

Volumn 51, Issue 3, 2007, Pages 398-404

  Kaur, Harsupreet ^a   Kabra, Sneha ^a   Bindra, Simrata ^a   Haldar, Subhasis ^b   Gupta, R S ^a  

^a UNIVERSITY OF DELHI   (India)

^b UNIVERSITY OF DELHI   (India)

Author keywords

Device modeling; Graded channel; Short channel effects; Surrounding gate MOSFET

Indexed keywords

DOPING (ADDITIVES); ELECTRIC FIELDS; GATES (TRANSISTOR); HOT CARRIERS; INTERFACES (MATERIALS); POISSON EQUATION; THRESHOLD VOLTAGE;

DEVICE MODELING; DEVICE SIMULATOR; DRAIN INDUCED BARRIER LOWERING (DIBL); GRADED CHANNEL; SHORT CHANNEL EFFECTS (SCE);

MOSFET DEVICES;

EID: 33947620692     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.01.025     Document Type: Article

References (28)

1. Yan R.H., Ourmazd A., and Lee K.F. Scaling the Si MOSFET: From Bulk to SOI to Bulk. IEEE Trans Electron Devices 39 (1992) 1704-1710
2. Takato H., Sunouchi K., Okabe N., Nitayama A., Hieda K., Horiguchi F., et al. Impact of Surrounding Gate Transistor (SGT) for Ultra-High-density LSI's. IEEE Trans Electron Devices 38 (1991) 573-578
3. Nitayami A., Takato H., Okabe N., Sunouchi K., Hiea K., Horiguchi F., et al. Multi-Pillar Surrounding Gate Transistor (M-SGT) for Compact and High-Speed Circuits. IEEE Trans Electron Devices 38 (1991) 579-583
4. Watanabe S., Tsuchida K., Takashima D., Oowaki Y., Nitayama A., Hieda K., et al. A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Utra High Density DRAM's. IEEE J Solid State Circuits 30 (1995) 960-971
5. Maeda S., Maegawa S., Ipposhi T., Nishimura H., Kuriyama H., Tanina O., et al. Impact of a Vertical Φ-Shape Transistor (VΦT) Cell for 1 Gbit DRAM and Beyond. IEEE Trans Electron Devices 42 (1995) 2117-2124
6. Okumura Y., Shirahata M., Hachisuka A., Okudaira T., Arima H., and Matsukawa T. Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability. IEEE Trans Electron Devices 39 (1992) 2541-2552
7. Odanaka S., and Hiroki A. Potential Design and Transport Property of 0.1 μm MOSFET with Asymmetric Channel Profile. IEEE Trans Electron Devices 44 (1997) 595-600
8. Cheng B., Rao V.R., and Woo J.C.S. Exploration of velocity overshoot in a high performance deep sub-0.1 μm SOI MOSFET with asymmetric channel profile. IEEE Trans Electron Devices Lett 20 (1999) 538-540
9. Shin H., and Lee S. A 0.1 μm Asymmetric Halo by Large-Angle-Tilt Implant (AHLATI) MOSFET for High Performance and Reliability. IEEE Trans Electron Devices 46 (1999) 820-822
10. Dehan M., and Raskin J.P. An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics. Solid State Electron 46 (2002) 1005-1011
11. Kranti A., Chung T.M., Flandre D., and Raskin J.P. Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications. Solid State Electron 48 (2004) 947-959
12. Pavanello M.A., Martino J.A., and Flandre D. Analog performance and application of graded channel fully depleted SOI MOSFETs. Solid State Electron 44 7 (2000) 1219-1222
13. Pavanello M.A., Martino J.A., and Flandre D. Analog circuit design using graded channel silicon-on insulator nMOSFETs. Solid State Electron 46 8 (2002) 1215-1225
14. Chen X., Ouyang Q.C., Wang G., and Banerjee S.K. Improved Hot-Carrier and Short-Channel Performance in Vertical nMOSFETs With Graded Channel Doping. IEEE Trans Electron Devices 49 (2002) 1962-1968
15. Auth C.P., and Plummer J.D. Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET's. IEEE Electron Device Lett 18 (1997) 74-76
16. Kranti A., Haldar S., and Gupta R.S. Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET. Microelectron Eng 56 (2001) 241-259
17. Nakamura H., Sakuraba H., and Masuoka F. NAND-type DRAM-on-SGT. IEEE Trans Electron Devices 52 (2005) 427-429
18. Iñi{dotless}́guez B., Jimenez D., Roig J., Hamid H.A., Marsal L.F., and Pallares J. Explicit continuous Model for Long-Channel Undoped Surrounding Gate MOSFETs. IEEE Trans Electron Devices 52 (2005) 1868-1873
19. Oh S.H., et al. Analytic description of short channel effects in fully depleted double gate and cylindrical, surrounding gate MOSFETs. IEEE Electron Device Lett 21 9 (2000) 445-447
20. Kranti A., et al. Design and optimization of thin film fully depleted vertical surrounding gate (VSG) MOSFETs for enhanced short channel immunity. Solid State Electron 46 9 (2002) 1333-1338
21. Young K. Short Channel Effect in Fully Depleted SOI MOSFET's. IEEE Trans Electron Devices 36 (1989) 399-402
22. SILVACO International, "ATLAS Users Manual 2000".
23. de Souza M., Pavanello M.A., Iñi{dotless}́guez B., and Flandre D. A charge based continuous model for submicron graded-channel nMOSFET for analog circuit simulation. Solid State Electron 49 (2005) 1683-1692
24. López J.A.V., Gámiz F., Roldán J.B., Ghailan Y., Carcellar J.E., and Cartujo P. Study of the effects of a stepped doping profile in short channel MOSFETs. IEEE Trans Electron Devices 44 9 (1997) 1425-1431
25. Baccarani G., and Reggiani S. A compact double-gate MOSFET model comprising quantum mechanical and nonstatic effects. IEEE Trans Electron Devices 8 46 (1999) 1656-1666
26. Naveh Y., and Likharev K.K. Modeling of 10 nm-scale ballistic MOSFETs. IEEE Trans Electron Device Lett 21 5 (2000) 242-244
27. Ren Z., Venugopal R., Datta S., and Lundstorm M. The ballistic nanotransistor: a simulation study. IEDM Tech Dig (2000) 715-718
28. ds). Solid State Electron 47 (2003) 155-159