Analog circuit design using graded-channel silicon-on-insulator nMOSFETs

Solid-State Electronics

Volumn 46, Issue 8, 2002, Pages 1215-1225

  Pavanello, Marcelo Antonio ^a,b   Antonio Martino, João ^a   Flandre, Denis ^c  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b UNIVERSITY OF CAMPINAS   (Brazil)

^c UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CONDUCTANCE; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

FULLY DEPLETED (FD) TRANSISTORS;

MOSFET DEVICES;

EID: 0036680370     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00020-5     Document Type: Article

References (17)

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3. Analog performance and application of graded-channel fully depleted SOI MOSFETs
4. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects
5. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics
6. Modeling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits
7. Improved LOCOS isolation for thin-film SOI MOSFETs
8. An MOS transistor model for analog circuit design
9. D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
10. Potential and modeling of 1 μm SOI CMOS operational transconductance amplifiers for applications up to 1 GHz
11. Measurement of intrinsic gate capacitances of SOI MOSFET's
12. Analysis of floating substrate effects on intrinsic gate capacitance of SOI MOSFET's using two-dimensional device simulation
13. High performance current-mirror using graded-channel SOI nMOSFET