Analog performance and application of graded-channel fully depleted SOI MOSFETs

Solid-State Electronics

Volumn 44, Issue 7, 2000, Pages 1219-1222

  Pavanello, Marcelo Antonio ^a   Martino, João Antonio ^a   Dessard, Vincent ^b   Flandre, Denis ^b  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

GRADED CHANNEL (GC) DEVICES; OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTA);

OPERATIONAL AMPLIFIERS;

EID: 0033751937     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(00)00034-4     Document Type: Article

References (9)

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3. Silveira F., Flandre D., Jespers P. A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE J Solid-State Circuits. 31(9):1996;1314-1319.
4. Pavanello M.A., Martino J.A., Dessard V., Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochem Solid-State Lett. 3(1):2000;50-52.
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9. Eggermont JP, Flandre D, Raskin JP, Colinge JP. Potential and modeling of 1 μm SOI CMOS operational transconductance amplifiers for applications up to 1 GHz. IEEE J Solid-State Circuits 1998;33(4):640-3.