Gain stage design based on narrow-width methodology in SOI technology

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1996, Pages 219-222

  Cheung, Denny T Y ^a   Lau, Jack ^a   Chan, Philip C H ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; FREQUENCY RESPONSE; OPERATIONAL AMPLIFIERS; OPTIMIZATION; SILICA; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

GRAIN STAGE DESIGN; MILLER COMPENSATION CAPACITANCE; NARROW WIDTH METHODOLOGY; PARASITIC CAPACITANCE REDUCTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029717201     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)