Impact of technology parameters on device performance of UTB-SOI CMOS

Solid-State Electronics

Volumn 48, Issue 4, 2004, Pages 521-527

  Schulz, T ^a   Pacha, C ^a   Luyken, R J ^a   Stadele M ^a   Hartwich, J ^a   Dreeskornfeld, L ^a   Landgraf, E ^a   Kretz, J ^a   Rosner W ^a   Specht, M ^a   Hofmann, F ^a   Risch, L ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Coupled device and circuit simulation; Mixed mode simulation; Nanometer scaled CMOS; Ultra thin body; Undoped SOI

Indexed keywords

CHARGE COUPLED DEVICES; COMPUTER SIMULATION; DIGITAL CIRCUITS; DOPING (ADDITIVES); ELECTRIC INSULATORS; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; ELECTRON TUNNELING; GATES (TRANSISTOR); ION IMPLANTATION; IONIZATION; MOSFET DEVICES; SILICON;

COUPLED DEVICE AND CIRCUIT SIMULATION; MIXED MODE SIMULATION; NANOMETER SCALED CMOS; ULTRATHIN BODY; UNDOPED SILICON ON INSULATORS (SOI);

CMOS INTEGRATED CIRCUITS;

EID: 10744221153     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.09.021     Document Type: Conference Paper

References (7)

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2. Luyken RJ, Städele M, Rösner W, Schulz T, Hartwich J, Dreeskornfeld L, et al. Perspectives of fully depleted SOI transistors down to 20 nm gate length. IEEE International SOI Conference, October 2002, p. 137-9.
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7. International Technology Roadmap for Semiconductors, 2001 Edition, Available from: http://public.itrs.net.