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Volumn 44, Issue 9, 2000, Pages 1621-1625

Ultra-thin midgap gate FDSOI MOSFET

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

EID: 0034272926     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(00)00107-6     Document Type: Article
Times cited : (22)

References (10)
  • 3
    • 0032315814 scopus 로고    scopus 로고
    • 40 nm gate length ultra-thin SOI n-MOSFET's with a backside conducting layer
    • Suzuki E, et al. 40 nm gate length ultra-thin SOI n-MOSFET's with a backside conducting layer. Dev Res Conf Dig 1998.
    • (1998) Dev Res Conf Dig
    • Suzuki, E.1
  • 4
    • 33746189368 scopus 로고
    • 0.1- μ m-gate ultrathin-film CMOS devices using SIMOX substrate with 80-nm thick buried oxide layer
    • Omura Y, Nakashima S, Izumi K, Ishii T. 0.1- μ m-gate ultrathin-film CMOS devices using SIMOX substrate with 80-nm thick buried oxide layer. IEDM Tech Dig 1991:675-8.
    • (1991) IEDM Tech Dig , pp. 675-678
    • Omura, Y.1    Nakashima, S.2    Izumi, K.3    Ishii, T.4
  • 5
    • 0020830319 scopus 로고
    • Threshold voltage of thin-film SOI MOSFET's
    • Lim H.K., Fossum J.G. Threshold voltage of thin-film SOI MOSFET's. IEEE Trans Electron Dev. 30(1):1983;1244.
    • (1983) IEEE Trans Electron Dev , vol.30 , Issue.1 , pp. 1244
    • Lim, H.K.1    Fossum, J.G.2
  • 6
    • 0025568096 scopus 로고
    • Adjustable confinement of the electron gas in dual-gate silicon-on-insulator MOSFET's
    • Cristoloveanu S., Ioannou D.E. Adjustable confinement of the electron gas in dual-gate silicon-on-insulator MOSFET's. Superlattices and Microstruct. 8(1):1990;131-135.
    • (1990) Superlattices and Microstruct , vol.8 , Issue.1 , pp. 131-135
    • Cristoloveanu, S.1    Ioannou, D.E.2
  • 7
    • 0029233869 scopus 로고
    • CMOS scaling in the 0.1 μ m, 1 X-volt regime for high-preformance applications
    • Shanhidi GG, et al. CMOS scaling in the 0.1 μ m, 1 X-volt regime for high-preformance applications. IBM J Res Develop 1995;39(1/2):229-62.
    • (1995) IBM J Res Develop , vol.39 , Issue.1-2 , pp. 229-262
    • Shanhidi, G.G.1
  • 8
    • 0032284102 scopus 로고    scopus 로고
    • Device design considerations for double-gate ground-plane, and single-gated ultra-thin SOI MOSFET's at 25 nm channel length generation
    • Wong HSP, Frank D, Solomon P. Device design considerations for double-gate ground-plane, and single-gated ultra-thin SOI MOSFET's at 25 nm channel length generation. IEDM Tech Dig 1998:407-10.
    • (1998) IEDM Tech Dig , pp. 407-410
    • Wong, H.S.P.1    Frank, D.2    Solomon, P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.