메뉴 건너뛰기




Volumn , Issue , 2004, Pages 878-883

Compact thermal modeling for temperature-aware design

Author keywords

Leakage; Power aware design; Reliability; Temperature aware computing; Temperature aware design; Thermal model

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; THERMAL EFFECTS;

EID: 4444374512     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996800     Document Type: Conference Paper
Times cited : (240)

References (20)
  • 2
    • 33646864552 scopus 로고    scopus 로고
    • Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
    • February
    • K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2):305-327, February 2003.
    • (2003) Proceedings of the IEEE , vol.91 , Issue.2 , pp. 305-327
    • Roy, K.1    Mukhopadhyay, S.2    Mahmoodi-Meimand, H.3
  • 4
    • 0242521368 scopus 로고    scopus 로고
    • IC thermal map from digital and thermal simulations
    • Oct.
    • K. Torki and F. Ciontu. IC thermal map from digital and thermal simulations. In Proc. 8th THERMINIC, pages 303-08, Oct. 2002.
    • (2002) Proc. 8th THERMINIC , pp. 303-308
    • Torki, K.1    Ciontu, F.2
  • 8
    • 0035691804 scopus 로고    scopus 로고
    • Two benchmarks to facilitate the study of compact thermal modeling phenomena
    • December
    • C. J. M. Lasance. Two benchmarks to facilitate the study of compact thermal modeling phenomena. Components and Packaging Technologies, IEEE Transactions on, 24(4):559-565, December 2001.
    • (2001) Components and Packaging Technologies, IEEE Transactions on , vol.24 , Issue.4 , pp. 559-565
    • Lasance, C.J.M.1
  • 9
    • 0036902415 scopus 로고    scopus 로고
    • Global coupled EM-electrical-thermal simulation and experimental validation for a spatial power combining MMIC array
    • Dec
    • W. Batty et al. Global coupled EM-electrical-thermal simulation and experimental validation for a spatial power combining MMIC array. Microwave Theory and Techniques, IEEE Transactions on, pages 2820-33, Dec. 2002.
    • (2002) Microwave Theory and Techniques, IEEE Transactions on , pp. 2820-2833
    • Batty, W.1
  • 10
    • 0032025118 scopus 로고    scopus 로고
    • The development of component-level thermal compact models of a C4/CBGA interconnect technology: The motorola PowerPC 603 and PowerPC 604 RISC microproceesors
    • March
    • J. Parry, H. Rosten, and G. B. Kromann. The development of component-level thermal compact models of a C4/CBGA interconnect technology: The motorola PowerPC 603 and PowerPC 604 RISC microproceesors. Components, Packaging, and Manufacturing Technology-Part A, IEEE Transactions on, 21(1):104-112, March 1998.
    • (1998) Components, Packaging, and Manufacturing Technology-part A, IEEE Transactions on , vol.21 , Issue.1 , pp. 104-112
    • Parry, J.1    Rosten, H.2    Kromann, G.B.3
  • 11
    • 0000551402 scopus 로고
    • Constricting/spreading resistance model for electronics packaging
    • March
    • S. Lee, S. Song, V. Au, and K. Moran. Constricting/spreading resistance model for electronics packaging. In Proc. AJTEC, pages 199-206, March 1995.
    • (1995) Proc. AJTEC , pp. 199-206
    • Lee, S.1    Song, S.2    Au, V.3    Moran, K.4
  • 13
    • 4444267154 scopus 로고    scopus 로고
    • Compact thermal modeling for temperature-aware design
    • Univ. of Virginia Dept. of Computer Science, April
    • W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. Compact thermal modeling for temperature-aware design. Tech Report CS-2004-13, Univ. of Virginia Dept. of Computer Science, April. 2004.
    • (2004) Tech Report , vol.CS-2004-13
    • Huang, W.1    Stan, M.R.2    Skadron, K.3    Sankaranarayanan, K.4    Ghosh, S.5    Velusamy, S.6
  • 14
    • 0032026510 scopus 로고    scopus 로고
    • A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation
    • March
    • J. A. Davis, V. K. De, and J. D. Meindl. A stochastic wire-length distribution for gigascale integration (GSI) - part I: Derivation and validation. Electron Devices, IEEE Transactions on, 45(3):580-589, March 1998.
    • (1998) Electron Devices, IEEE Transactions on , vol.45 , Issue.3 , pp. 580-589
    • Davis, J.A.1    De, V.K.2    Meindl, J.D.3
  • 18
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
    • May
    • K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat. 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, 89(5):602-633, May 2001.
    • (2001) Proceedings of the IEEE , vol.89 , Issue.5 , pp. 602-633
    • Banerjee, K.1    Souri, S.J.2    Kapur, P.3    Saraswat, K.C.4
  • 19
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • June
    • D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. ISCA-27, pages 83-94, June 2000.
    • (2000) Proc. ISCA-27 , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.