Clock distribution network optimization under self-heating and timing constraints

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2451, Issue , 2002, Pages 198-208

  Casu, M R ^a   Graziano, M ^a   Masera, G ^a   Piccinini, G ^a   Prono, M M ^a   Zamboni, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; TIMING CIRCUITS;

CLOCK NETWORK; DEEP SUB-MICRON; ELECTRICAL ANALYSIS; ITS APPLICATIONS; SELF-HEATING; TIMING CONSTRAINTS;

CLOCK DISTRIBUTION NETWORKS;

EID: 84943223299     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45716-x_20     Document Type: Conference Paper

References (15)

1. A. H. Ajami, M. Pedram, and K. Banerjee. Effects on non-uniform substrate temperature on the clock signal integrity in high performance designs. IEEE 2001 Custom Integrated Circuits Conference, 2001.
2. S. I. Assoc. International Technology Roadmap for Semiconductors. Technical report, 2001.
3. Avant! Corporation. Avant! Star-HSpice User’s Manual.
4. R. M. Averill et al. Chip integration methodology for the IBM S/390 G5 and G6 customm icroprocessors. IBM J. Res. Develop., 43(5/6), 1999.
5. M. Casu, M. Graziano, G. Masera, G. Piccinini, and M. Zamboni. Power supply bus sizing considering self-heating in bulk-to-soi migrated designs. PATMOS – Power And Timing Modeling, Optimization and Simulation, 2001.
6. D. Chen, E. Li, E. Rosenbaum, and S.-M. Kang. Interconnect thermal modeling for accurate simulation of circuit timing and reliability. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 19(2), 2000.
7. J. Cong, A. B. Kahng, D. Noice, N. Shirali, and S. H.-C. Yen. Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology. Design Automation Conference, 1997.
8. Y. Ismail and E. Friedman. On-chip inductance in high speed integrated circuits. Kluwer Academic Publishers, Massachusetts, 2001.
9. M. Kamon, M. J. Tsuk, and J. K. White. FastHenry: A multiple accelerated 3- D inductance extraction program. IEEE Transactions on Microwave Theory and Techniques, 42(9), 1994.
10. W. H. Kao, C.-Y. Lo, M. Basel, and R. Singh. Parasitic extraction: Current state of the art and future trends. Proceedings of the IEEE, 89(5):729–739, 2001.
11. J. L. Maksiejewski. Evaluation of thermal characteristics of conductors under surge currents taking the skin effect into account. IEE Proc., 137(2):85–91, 1990.
12. K. Nabors and J. White. FastCap: A multiple accelerated 3-D capacitance extraction program. IEEE Transactions on Computer-Aided Design, 10(11), 1991.
13. M. M. Prono. Techniques for high speed interconnect design. Master thesis, University of Illinois at Chicago, 2001.
14. S. D. Systems. Thunder user’s manual. Technical report, 1993.
15. C.-C. Teng, Y.-K. Cheng, E. Rosenbaum, and S.-M. Kang. iTEM: A temperaturedependent electromigration reliability diagnosis tool. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 16(8), 1997.