An electromigration and thermal model of power wires for a priori high-level reliability prediction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 4, 2004, Pages 349-358

  Casu, Mario R ^a   Graziano, Mariagrazia ^a   Masera, Guido ^a   Piccinini, Gianluca ^a   Zamboni, Maurizio ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Apriori power supply interconnect prediction; Electromigration (EM) estimation; Self consistent roadmap projections; Statistical current model

Indexed keywords

APRIORI POWER SUPPLY INTERCONNECT PREDICTION; ELECTROMIGRATION (EM) ESTIMATION; SELF CONSISTENT ROADMAP PROJECTION; STATISTICAL CURRENT MODELS;

ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRIC POWER SYSTEMS; HEATING; MATHEMATICAL MODELS; RELIABILITY; STATISTICAL METHODS; THERMAL CONDUCTIVITY; VLSI CIRCUITS;

ELECTROMIGRATION;

EID: 2442674444     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.825599     Document Type: Article

References (25)

1. H. B. Bakoglu, Circuits Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990, ch. 9.
2. B. Geuskens and K. Rose, Modeling Microprocessor Performance. Norwell, MA: Kluwer, 1998.
3. D. Sylvester and C. Hu, "Analytical modeling and characterization of deep-submicrometer interconnect," Proc. IEEE, vol. 89, May 2001.
4. J. C. Eble, "A Generic System Simulator With Novel On-Chip Cache and Throughput Models for Gigascale Integration," Ph.D. dissertation, Georgia Inst. Tech, Atlanta, GA, 1998.
5. A. E. Caldwell et al., "GTX: The MARCO GSRC technology extrapolation system," in Proc. DAC, 2000, pp. 693-698.
6. K. Banerjee and A. Merhotra, "Global (interconnect) warming," IEEE Circ. Dev. Mag., pp. 16-32, Sept. 2001.
7. M. R. Casu et al., "Clock distribution network optimization under self-heating and timing constraints," in Proc. PATMOS, 2002, pp. 198-208.
8. D. T. Blaauw, "Static electromigration analysis for on-chip signal interconnects," IEEE Trans. Computer-Aided Design, vol. 22, pp. 39-48, Jan. 2003.
9. J. R. Black, "Electromigration-a brief survey and some recent results," IEEE Trans. Electron Devices, vol. ED-16, pp. 338-347, Apr. 1974.
10. W. R. Hunter, "Self-consistent solutions for allowed interconnect current density-Part I: Implications for technology evolution," IEEE Trans. Electron Devices, vol. 44, pp. 304-309, Feb. 1997.
11. K. Banerjee et al., "On thermal effects in deep sub-micron VLSI interconnects," in Proc. DAC, 1999, pp. 885-891.
12. C. Teng et al., "Item: A temperature-dependent electromigration reliability diagnosis tool," IEEE Trans. Computer-Aided Design, vol. 16, pp. 882-893, Aug. 1997.
13. D. Chen, "Interconnect thermal modeling for accurate simulation of circuit timing and reliability," IEEE Trans. Computer-Aided Design, vol. 19, pp. 197-205, Feb. 2000.
14. "The International Technology Roadmap for Semiconductors," SIA., 2001.
15. P. Zarkesh-Ha et al., "Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip," IEEE Trans. VLSI Syst., vol. 8, pp. 649-659, Dec. 2000.
16. P. Christie and D. Stroobandt, "The interpretation and application of rent's rule," IEEE Trans. VLSI Syst., vol. 8, pp. 639-648, Dec. 2000.
17. D. Sylvester and K. Keutzer, "Impact of small process geometries in system on chip," Proc. IEEE, vol. 89, Apr. 2001.
18. BACPAC: The Berkeley Advanced Chip Performance Calculator. [Online]. Available: http://www.device.eecs.berkeley.edu/~dennis/BACPAC
19. P. Kapur et al., "Technology and reliability constrained future copper interconnects-Part I: Resistance modeling," IEEE Trans. Electron Devices, vol. 49, pp. 590-597, Apr. 2002.
20. M. R. Casu et al., "Power supply wire sizing considering self-heating in bulk-to-SOI migrated designs," in Proc. PATMOS. 2001, pp. 8.3.1-8.3.10.
21. W. E. Donath, "Wire length distribution for placements of computer logic," IBM J. Res. Develop., vol. 25, pp. 152-155, May 1981.
22. J. A. Davis et al., "A stocastic wire length distribution for gigascale integration (GSI) - Part I: Derivation and validation," IEEE Trans. Electron Devices, vol. 45, pp. 580-589, Mar. 1998.
23. P. Zarkesh-Ha, "Global interconnect modeling for a gigascale system-on-a-chip (GSoC)," Ph.D. dissertation, Georgia Inst. Tech., Atlanta, GA, 2001.
24. GTX: The MARCO GSRC Technology Extrapolation System. [Online]. Available: http://nexus6.cs.ucla.edu/GSRC/GTX
25. D. M. Sylvester, "Analytical Modeling and Characterization of Deep Submicron Interconnect," Ph.D. dissertation, Univ. Calif., Berkeley, 1999.